Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s core/riscv/riscv_alu.v core/riscv/riscv_core.v core/riscv/riscv_csr.v core/riscv/riscv_csr_regfile.v core/riscv/riscv_decode.v core/riscv/riscv_decoder.v core/riscv/riscv_defs.v core/riscv/riscv_divider.v core/riscv/riscv_exec.v core/riscv/riscv_fetch.v core/riscv/riscv_issue.v core/riscv/riscv_lsu.v core/riscv/riscv_mmu.v core/riscv/riscv_multiplier.v core/riscv/riscv_pipe_ctrl.v core/riscv/riscv_regfile.v core/riscv/riscv_trace_sim.v core/riscv/riscv_xilinx_2r1w.v top_cache_axi/src_v/dcache.v top_cache_axi/src_v/dcache_axi.v top_cache_axi/src_v/dcache_axi_axi.v top_cache_axi/src_v/dcache_core.v top_cache_axi/src_v/dcache_core_data_ram.v top_cache_axi/src_v/dcache_core_tag_ram.v top_cache_axi/src_v/dcache_if_pmem.v top_cache_axi/src_v/dcache_mux.v top_cache_axi/src_v/dcache_pmem_mux.v top_cache_axi/src_v/icache.v top_cache_axi/src_v/icache_data_ram.v top_cache_axi/src_v/icache_tag_ram.v top_cache_axi/src_v/riscv_top.v top_tcm_axi/src_v/dport_axi.v top_tcm_axi/src_v/dport_mux.v top_tcm_axi/src_v/riscv_tcm_top.v top_tcm_axi/src_v/tcm_mem.v top_tcm_axi/src_v/tcm_mem_pmem.v top_tcm_axi/src_v/tcm_mem_ram.v top_tcm_wrapper/dport_axi.v top_tcm_wrapper/dport_mux.v top_tcm_wrapper/riscv_tcm_wrapper.v top_tcm_wrapper/tcm_mem.v top_tcm_wrapper/tcm_mem_pmem.v top_tcm_wrapper/tcm_mem_ram.v
core/riscv/riscv_csr.v:100: Include file riscv_defs.v not found
core/riscv/riscv_csr.v:99: syntax error
I give up.