Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (47 sec in block)
node - (46 sec in block)
node block - (46 sec in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.3 sec in block)
sh - (0.45 sec in self)rm -rf *.xml
sh - (0.45 sec in self)rm -rf rsd
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/rsd-devel/rsd rsd
stage - (1.3 sec in block)Simulation
stage block (Simulation) - (0.89 sec in block)
dir - (0.54 sec in block)rsd
dir block - (0.31 sec in block)
echo - (0.1 sec in self)FPGA > Simulation
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.83 sec in block)rsd
dir block - (0.6 sec in block)
sh - (0.4 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (39 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (38 sec in block)
parallel - (38 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (37 sec in block)
stage - (37 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (37 sec in block)
lock - (36 sec in block)digilent_arty_a7_100t
lock block - (35 sec in block)
stage - (34 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (33 sec in block)
dir - (33 sec in block)rsd
dir block - (32 sec in block)
echo - (0.15 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (32 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rsd -b digilent_arty_a7_100t
stage - (0.87 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.33 sec in block)
getContext - (0.15 sec in self)
stage - (0.66 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.37 sec in block)
getContext - (0.16 sec in self)
stage - (0.74 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.52 sec in block)
junit - (0.26 sec in self)**/*.xml