Skip to content
StepArgumentsStatus
Start of Pipeline - (4 min 18 sec in block)
node - (4 min 15 sec in block)
node block - (4 min 14 sec in block)
stage - (6.6 sec in block)Git Clone
stage block (Git Clone) - (5.3 sec in block)
sh - (0.67 sec in self)rm -rf *.xml
sh - (1.9 sec in self)rm -rf rvx
sh - (2.4 sec in self)git clone --recursive --depth=1 https://github.com/rafaelcalcada/rvx rvx
stage - (8.4 sec in block)Simulation
stage block (Simulation) - (5.2 sec in block)
dir - (3.1 sec in block)rvx
dir block - (1.6 sec in block)
echo - (0.76 sec in self)FPGA > Simulation
stage - (8.7 sec in block)Utilities
stage block (Utilities) - (6.8 sec in block)
dir - (4.6 sec in block)rvx
dir block - (3.6 sec in block)
sh - (2.2 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (3 min 47 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (3 min 45 sec in block)
parallel - (3 min 44 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (3 min 43 sec in block)
stage - (3 min 41 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3 min 40 sec in block)
lock - (3 min 38 sec in block)digilent_arty_a7_100t
lock block - (3 min 35 sec in block)
stage - (3 min 27 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 26 sec in block)
dir - (3 min 25 sec in block)rvx
dir block - (3 min 24 sec in block)
echo - (1.2 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (3 min 22 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rvx -b digilent_arty_a7_100t
stage - (4.2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (3 sec in block)
dir - (2.1 sec in block)rvx
dir block - (1.5 sec in block)
echo - (0.31 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (0.87 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rvx -b digilent_arty_a7_100t -l
stage - (1.3 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.83 sec in block)
getContext - (0.37 sec in self)
stage - (2.6 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.2 sec in block)
junit - (1.7 sec in self)**/*.xml