Skip to content
[Jenkins]Jenkins
log in
StepArgumentsStatus
Start of Pipeline - (5 min 48 sec in block)
node - (5 min 47 sec in block)
node block - (5 min 14 sec in block)
stage - (2.7 sec in block)Git Clone
stage block (Git Clone) - (2.2 sec in block)
sh - (0.58 sec in self)rm -rf serv
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/olofk/serv serv
stage - (1.9 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (0.88 sec in block)serv
dir block - (0.63 sec in block)
sh - (0.41 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.86 sec in block)serv
dir block - (0.62 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (5 min 6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 5 sec in block)
parallel - (5 min 5 sec in block)
parallel block (Branch: colorlight_i9) - (51 ms in block)
stage - (3 min 41 sec in block)colorlight_i9
stage block (colorlight_i9) - (3 min 41 sec in block)
lock - (3 min 40 sec in block)colorlight_i9
lock block - (3 min 40 sec in block)
stage - (3 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 23 sec in block)
dir - (3 min 22 sec in block)serv
dir block - (3 min 22 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (3 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b colorlight_i9
stage - (14 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (13 sec in block)
dir - (13 sec in block)serv
dir block - (12 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (12 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.4 sec in block)
echo - (0.21 sec in self)Testing FPGA colorlight_i9.
dir - (0.87 sec in block)serv
dir block - (0.6 sec in block)
sh - (0.41 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (5 min 5 sec in block)
stage - (5 min 4 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (5 min 4 sec in block)
lock - (5 min 3 sec in block)digilent_nexys4_ddr
lock block - (5 min 2 sec in block)
stage - (4 min 53 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4 min 53 sec in block)
dir - (4 min 52 sec in block)serv
dir block - (4 min 52 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (4 min 51 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b digilent_nexys4_ddr
stage - (7 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.6 sec in block)
dir - (6.2 sec in block)serv
dir block - (5.9 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_nexys4_ddr.
sh - (5.6 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b digilent_nexys4_ddr -l
stage - (1.6 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (1.3 sec in block)
echo - (0.22 sec in self)Testing FPGA digilent_nexys4_ddr.
dir - (0.85 sec in block)serv
dir block - (0.6 sec in block)
sh - (0.4 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.54 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml