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+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s FPGA_Implementation_AXI_peripheral/MAXI_ip.v FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v FPGA_Implementation_AXI_peripheral/SAXI_ip.v FPGA_Implementation_AXI_peripheral/caches.v FPGA_Implementation_AXI_peripheral/cpu.v FPGA_Implementation_AXI_peripheral/custom.v FPGA_Implementation_AXI_peripheral/system.v Benchmarks/simple_vector_add/custom.v RTL_and_simulation/caches.v RTL_and_simulation/cpu.v RTL_and_simulation/custom.v RTL_and_simulation/system.v RTL_and_simulation/testbench.v
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:17: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:18: warning: macro DL2block_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:49: warning: macro DADDR_bits undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:50: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:51: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:51: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:52: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:53: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:53: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:185: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:187: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:368: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:368: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:403: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:403: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:404: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:404: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:427: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:427: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:31: warning: macro DADDR_bits undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:32: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:33: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:33: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:34: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:35: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:35: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:FPGA_Implementation_AXI_peripheral/SAXI_ip.v:546: 17warning: macro IADDR_bits undefined (and assumed null) at this point.
: syntax errorFPGA_Implementation_AXI_peripheral/SAXI_ip.v:547: 
warning: macro DADDR_bits undefined (and assumed null) at this point.
I give up.