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Start of Pipeline - (24 sec in block)
node - (23 sec in block)
node block - (22 sec in block)
stage - (10 sec in block)Git Clone
stage block (Git Clone) - (10 sec in block)
sh - (0.58 sec in self)rm -rf *.xml
sh - (2.4 sec in self)rm -rf starsea_riscv
sh - (6.9 sec in self)git clone --recursive --depth=1 https://github.com/kisssko/starsea_riscv starsea_riscv
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.98 sec in block)
dir - (0.6 sec in block)starsea_riscv
dir block - (0.33 sec in block)
echo - (0.11 sec in self)FPGA > Simulation
stage - (2.3 sec in block)Utilities
stage block (Utilities) - (1.6 sec in block)
dir - (1.1 sec in block)starsea_riscv
dir block - (0.79 sec in block)
sh - (0.53 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (6.2 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.5 sec in block)
getContext - (0.29 sec in self)
parallel - (4.8 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.4 sec in block)
stage - (3.9 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (3.6 sec in block)
getContext - (0.41 sec in self)
stage - (0.97 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (1.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.43 sec in block)
getContext - (0.21 sec in self)
stage - (0.74 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.4 sec in block)
getContext - (0.17 sec in self)
stage - (0.86 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.61 sec in block)
junit - (0.34 sec in self)**/*.xml