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Start of Pipeline - (12 min in block)
node - (12 min in block)
node block - (8 min 25 sec in block)
stage - (2.7 sec in block)Git Clone
stage block (Git Clone) - (2.3 sec in block)
sh - (0.58 sec in self)rm -rf *.xml
sh - (0.44 sec in self)rm -rf potato
sh - (0.9 sec in self)git clone --recursive --depth=1 https://github.com/skordal/potato potato
stage - (1.6 sec in block)Simulation
stage block (Simulation) - (1.1 sec in block)
dir - (0.83 sec in block)potato
dir block - (0.59 sec in block)
sh - (0.39 sec in self)ghdl -a --std=08 src/pp_types.vhd src/pp_constants.vhd src/pp_utilities.vhd src/pp_csr.vhd src/pp_counter.vhd src/pp_csr_unit.vhd src/pp_register_file.vhd src/pp_fetch.vhd src/pp_imm_decoder.vhd src/pp_alu_control_unit.vhd src/pp_control_unit.vhd src/pp_decode.vhd src/pp_alu_mux.vhd src/pp_comparator.vhd src/pp_alu.vhd src/pp_csr_alu.vhd src/pp_execute.vhd src/pp_memory.vhd src/pp_writeback.vhd src/pp_core.vhd src/pp_icache.vhd src/pp_wb_adapter.vhd src/pp_wb_arbiter.vhd src/pp_potato.vhd
stage - (1.5 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.8 sec in block)potato
dir block - (0.59 sec in block)
sh - (0.38 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (8 min 17 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (8 min 17 sec in block)
parallel - (8 min 16 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (8 min 16 sec in block)
stage - (8 min 15 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (8 min 14 sec in block)
lock - (8 min 14 sec in block)digilent_arty_a7_100t
lock block - (3 min 42 sec in block)
stage - (3 min 38 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 38 sec in block)
dir - (3 min 37 sec in block)potato
dir block - (3 min 37 sec in block)
echo - (0.31 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (3 min 36 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p potato -b digilent_arty_a7_100t
stage - (2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (1.5 sec in block)
dir - (1 sec in block)potato
dir block - (0.78 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (0.44 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p potato -b digilent_arty_a7_100t -l
stage - (0.64 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.72 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.49 sec in block)
junit - (0.25 sec in self)**/*.xml