Console Output

+ iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/tinyriscv.v
rtl/core/if_id.v:41: error: Unknown module type: gen_pipe_dff
rtl/core/if_id.v:45: error: Unknown module type: gen_pipe_dff
rtl/core/if_id.v:49: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:60: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:64: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:68: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:72: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:76: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:80: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:84: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:88: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:92: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:96: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:100: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:104: error: Unknown module type: gen_pipe_dff
rtl/core/id_ex.v:108: error: Unknown module type: gen_pipe_dff
17 error(s) during elaboration.
*** These modules were missing:
        gen_pipe_dff referenced 16 times.
***