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Start of Pipeline - (15 min in block)
node - (15 min in block)
node block - (15 min in block)
stage - (3.5 sec in block)Git Clone
stage block (Git Clone) - (3 sec in block)
sh - (0.49 sec in self)rm -rf tinyriscv
sh - (2.2 sec in self)git clone --recursive https://github.com/liangkangnan/tinyriscv tinyriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.84 sec in block)tinyriscv
dir block - (0.6 sec in block)
sh - (0.4 sec in self)iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v
stage - (15 min in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (15 min in block)
parallel - (15 min in block)
parallel block (Branch: colorlight_i9) - (67 ms in block)
stage - (10 min in block)colorlight_i9
stage block (colorlight_i9) - (10 min in block)
lock - (10 min in block)colorlight_i9
lock block - (7 min 35 sec in block)
stage - (7 min 8 sec in block)Síntese e PnR
stage block (Síntese e PnR) - (7 min 8 sec in block)
dir - (7 min 7 sec in block)tinyriscv
dir block - (7 min 7 sec in block)
echo - (0.22 sec in self)Iniciando síntese para FPGA colorlight_i9.
sh - (7 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9
stage - (19 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (19 sec in block)
dir - (19 sec in block)tinyriscv
dir block - (18 sec in block)
echo - (0.16 sec in self)FPGA colorlight_i9 bloqueada para flash.
sh - (18 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9 -l
stage - (6.2 sec in block)Teste colorlight_i9
stage block (Teste colorlight_i9) - (6 sec in block)
echo - (0.21 sec in self)Testando FPGA colorlight_i9.
dir - (5.4 sec in block)tinyriscv
dir block - (5.2 sec in block)
sh - (5 sec in self)PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py
parallel block (Branch: digilent_nexys4_ddr) - (15 min in block)
stage - (15 min in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (15 min in block)
lock - (15 min in block)digilent_nexys4_ddr
lock block - (11 min in block)
stage - (10 min in block)Síntese e PnR
stage block (Síntese e PnR) - (10 min in block)
dir - (10 min in block)tinyriscv
dir block - (10 min in block)
echo - (0.31 sec in self)Iniciando síntese para FPGA digilent_nexys4_ddr.
sh - (10 min in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr
stage - (14 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (13 sec in block)
dir - (13 sec in block)tinyriscv
dir block - (12 sec in block)
echo - (0.17 sec in self)FPGA digilent_nexys4_ddr bloqueada para flash.
sh - (12 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr -l
stage - (1.4 sec in block)Teste digilent_nexys4_ddr
stage block (Teste digilent_nexys4_ddr) - (0.95 sec in block)
echo - (0.2 sec in self)Testando FPGA digilent_nexys4_ddr.
dir - (0.42 sec in block)tinyriscv
dir block - (0.16 sec in block)
stage - (1 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.77 sec in block)
junit - (0.57 sec in self)**/test-reports/*.xml