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Start of Pipeline - (5 min 7 sec in block)
node - (5 min 6 sec in block)
node block - (4 min 54 sec in block)
stage - (3.7 sec in block)Git Clone
stage block (Git Clone) - (3.2 sec in block)
sh - (0.59 sec in self)rm -rf *.xml
sh - (0.97 sec in self)rm -rf tinyriscv
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (1 sec in block)tinyriscv
dir block - (0.8 sec in block)
sh - (0.61 sec in self)iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v
stage - (7.5 sec in block)Utilities
stage block (Utilities) - (7.1 sec in block)
dir - (6.8 sec in block)tinyriscv
dir block - (6.5 sec in block)
sh - (6.3 sec in self) python3 -m venv tmp_venv bash -c "source tmp_venv/bin/activate" echo $VIRTUAL_ENV which python3 tmp_venv/bin/pip install cocotb tmp_venv/bin/python3 /eda/processor_ci_verification/regfile_finder.py -m /eda/processor_ci_utils/cores_utils/tinyriscv/tinyriscv.mk -o /eda/processor_ci_verification/output
stage - (4 min 40 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 39 sec in block)
parallel - (4 min 39 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 min 38 sec in block)
stage - (4 min 38 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 min 37 sec in block)
lock - (4 min 36 sec in block)digilent_arty_a7_100t
lock block - (2 min 42 sec in block)
stage - (2 min 38 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (2 min 38 sec in block)
dir - (2 min 37 sec in block)tinyriscv
dir block - (2 min 37 sec in block)
echo - (0.32 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (2 min 36 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p tinyriscv -b digilent_arty_a7_100t
stage - (2.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (1.5 sec in block)
dir - (1 sec in block)tinyriscv
dir block - (0.78 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (0.44 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p tinyriscv -b digilent_arty_a7_100t -l
stage - (0.65 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.71 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.48 sec in block)
junit - (0.25 sec in self)**/*.xml