Console Output
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9
Sending interrupt signal to process
Final configuration file generated at /var/jenkins_home/workspace/tinyriscv@2/tinyriscv/build_colorlight_i9.tcl
Error executing Makefile.
Info: constraining clock net 'sck' to 10.00 MHz
Info: constraining clock net 'clk' to 25.00 MHz
Info: Logic utilisation before packing:
Info: Total LUT4s: 15668/43848 35%
Info: logic LUTs: 8316/43848 18%
Info: carry LUTs: 992/43848 2%
Info: RAM LUTs: 4240/ 5481 77%
Info: RAMW LUTs: 2120/10962 19%
Info: Total DFFs: 1630/43848 3%
Info: Packing IOs..
Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'sck$tr_io' constrained to Bel 'X4/Y71/PIOA'.
Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'rw$tr_io' constrained to Bel 'X4/Y71/PIOB'.
Info: pin 'reset$tr_io' constrained to Bel 'X6/Y71/PIOB'.
Info: pin 'mosi$tr_io' constrained to Bel 'X9/Y71/PIOA'.
Info: pin 'miso$tr_io' constrained to Bel 'X0/Y65/PIOB'.
Info: pin 'intr$tr_io' constrained to Bel 'X9/Y71/PIOB'.
Info: pin 'cs$tr_io' constrained to Bel 'X6/Y71/PIOA'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 1054 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: promoting clock net clk_core to global network
Info: Checksum: 0x54f4faac
Info: Device utilisation:
Info: TRELLIS_IO: 10/ 245 4%
Info: DCCA: 2/ 56 3%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 4/ 72 5%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 1630/ 43848 3%
Info: TRELLIS_COMB: 15824/ 43848 36%
Info: TRELLIS_RAMW: 1060/ 5481 19%
Info: Placed 10 cells based on constraints.
Info: Creating initial analytic placement for 8032 cells, random placement wirelen = 748864.
Info: at initial placer iter 0, wirelen = 2163
Info: at initial placer iter 1, wirelen = 2358
Info: at initial placer iter 2, wirelen = 2293
Info: at initial placer iter 3, wirelen = 2030
Info: Running main analytical placer, max placement attempts per cell = 42920112.
Info: at iteration #1, type ALL: wirelen solved = 2249, spread = 153562, legal = 154305; time = 0.47s
Info: at iteration #2, type ALL: wirelen solved = 10100, spread = 108207, legal = 110577; time = 0.57s
Info: at iteration #3, type ALL: wirelen solved = 21544, spread = 101511, legal = 102933; time = 0.52s
Info: at iteration #4, type ALL: wirelen solved = 27298, spread = 87832, legal = 89758; time = 0.50s
Info: at iteration #5, type ALL: wirelen solved = 31737, spread = 82790, legal = 85592; time = 0.49s
Info: at iteration #6, type ALL: wirelen solved = 34830, spread = 79900, legal = 83410; time = 0.50s
Info: at iteration #7, type ALL: wirelen solved = 38653, spread = 73638, legal = 76908; time = 0.48s
Info: at iteration #8, type ALL: wirelen solved = 39348, spread = 72448, legal = 76829; time = 0.45s
Info: at iteration #9, type ALL: wirelen solved = 41236, spread = 71825, legal = 77236; time = 0.46s
Info: at iteration #10, type ALL: wirelen solved = 42306, spread = 73347, legal = 78528; time = 0.47s
Info: at iteration #11, type ALL: wirelen solved = 45027, spread = 70319, legal = 75372; time = 0.44s
Info: at iteration #12, type ALL: wirelen solved = 45728, spread = 71047, legal = 76358; time = 0.46s
Info: at iteration #13, type ALL: wirelen solved = 46540, spread = 70170, legal = 77172; time = 0.51s
Info: at iteration #14, type ALL: wirelen solved = 47190, spread = 71075, legal = 77759; time = 0.55s
Info: at iteration #15, type ALL: wirelen solved = 48639, spread = 72851, legal = 76431; time = 0.49s
Info: at iteration #16, type ALL: wirelen solved = 50523, spread = 70853, legal = 75938; time = 0.43s
Info: HeAP Placer Time: 13.30s
Info: of which solving equations: 7.65s
Info: of which spreading cells: 1.06s
Info: of which strict legalisation: 0.37s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 16398, wirelen = 75372
make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:7: colorlight_i9.config] Terminated
Traceback (most recent call last):
File "/eda/processor-ci/main.py", line 135, in <module>
main(
File "/eda/processor-ci/main.py", line 82, in main
build(build_file_path, board_name, toolchain_path)
File "/eda/processor-ci/core/fpga.py", line 215, in build
raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
script returned exit code 1
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