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Start of Pipeline - (7 min 45 sec in block)
node - (7 min 44 sec in block)
node block - (7 min 44 sec in block)
stage - (2.8 sec in block)Git Clone
stage block (Git Clone) - (2.3 sec in block)
sh - (0.45 sec in self)rm -rf tinyriscv
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.87 sec in block)tinyriscv
dir block - (0.6 sec in block)
sh - (0.42 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.87 sec in block)tinyriscv
dir block - (0.65 sec in block)
sh - (0.42 sec in self)python3 /eda/processor-ci/labeler_prototype.py -d $(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (7 min 36 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (7 min 36 sec in block)
parallel - (7 min 35 sec in block)
parallel block (Branch: colorlight_i9) - (50 ms in block)
stage - (3 min 29 sec in block)colorlight_i9
stage block (colorlight_i9) - (3 min 29 sec in block)
lock - (3 min 28 sec in block)colorlight_i9
lock block - (3 min 27 sec in block)
stage - (3 min 8 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 8 sec in block)
dir - (3 min 7 sec in block)tinyriscv
dir block - (3 min 7 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (3 min 6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9
stage - (16 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (16 sec in block)
dir - (15 sec in block)tinyriscv
dir block - (15 sec in block)
echo - (0.17 sec in self)Flashing FPGA colorlight_i9.
sh - (15 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9 -l
stage - (1.6 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.3 sec in block)
echo - (0.21 sec in self)Testing FPGA colorlight_i9.
dir - (0.84 sec in block)tinyriscv
dir block - (0.58 sec in block)
sh - (0.39 sec in self)echo "Test for FPGA in /dev/ttyACM0"
parallel block (Branch: digilent_nexys4_ddr) - (7 min 35 sec in block)
stage - (7 min 34 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (7 min 34 sec in block)
lock - (7 min 33 sec in block)digilent_nexys4_ddr
lock block - (7 min 32 sec in block)
stage - (7 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (7 min 23 sec in block)
dir - (7 min 22 sec in block)tinyriscv
dir block - (7 min 22 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (7 min 21 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr
stage - (7.5 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (6.9 sec in block)
dir - (6.4 sec in block)tinyriscv
dir block - (6 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_nexys4_ddr.
sh - (5.6 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr -l
stage - (0.69 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.39 sec in block)
getContext - (0.16 sec in self)
stage - (0.78 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.55 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml