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Start of Pipeline - (3 min 3 sec in block)
node - (3 min 1 sec in block)
node block - (2 min 35 sec in block)
stage - (2 min 24 sec in block)Git Clone
stage block (Git Clone) - (2 min 23 sec in block)
sh - (0.66 sec in self)rm -rf *.xml
sh - (0.68 sec in self)rm -rf Cores-SweRV
sh - (2 min 21 sec in self)git clone --recursive --depth=1 https://github.com/chipsalliance/Cores-SweRV Cores-SweRV
stage - (1.2 sec in block)Verilog Convert
stage block (Verilog Convert) - (0.41 sec in block)
getContext - (0.2 sec in self)
stage - (1.2 sec in block)Simulation
stage block (Simulation) - (0.58 sec in block)
getContext - (0.21 sec in self)
stage - (1 sec in block)Utilities
stage block (Utilities) - (0.39 sec in block)
getContext - (0.17 sec in self)
stage - (6.6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5.9 sec in block)
getContext - (0.33 sec in self)
parallel - (5.2 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4.8 sec in block)
stage - (4.3 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 sec in block)
getContext - (0.53 sec in self)
stage - (1.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.41 sec in block)
getContext - (0.19 sec in self)
stage - (1.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.47 sec in block)
getContext - (0.24 sec in self)
stage - (0.72 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.17 sec in self)
stage - (0.91 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.65 sec in block)
junit - (0.38 sec in self)**/*.xml