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| Step | Arguments | Status | ||
|---|---|---|---|---|
| Start of Pipeline - (5.2 sec in block) | ||||
| node - (4.8 sec in block) | ||||
| node block - (4.4 sec in block) | ||||
| stage - (3.4 sec in block) | git_clone | |||
| stage block (git_clone) - (3.1 sec in block) | ||||
| sh - (0.39 sec in self) | rm -Rf dv-cpu-rv/ build/ | |||
| sh - (2.2 sec in self) | git clone https://github.com/devindang/dv-cpu-rv.git | |||
| sh - (0.35 sec in self) | cd dv-cpu-rv | |||
| stage - (0.77 sec in block) | Yosys | |||
| stage block (Yosys) - (0.57 sec in block) | ||||
| sh - (0.41 sec in self) | /eda/oss-cad-suite/bin/yosys -p " read_verilog dv-cpu-rv/core/rtl/*.v synth -json ./build/out.json -abc9 -top rv_core " |