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Start of Pipeline - (1 min 15 sec in block)
node - (1 min 14 sec in block)
node block - (42 sec in block)
stage - (3.9 sec in block)Git Clone
stage block (Git Clone) - (3.4 sec in block)
sh - (0.57 sec in self)rm -rf *.xml
sh - (0.73 sec in self)rm -rf DV-CPU-RV
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/devindang/dv-cpu-rv.git DV-CPU-RV
stage - (1.7 sec in block)Simulation
stage block (Simulation) - (1.2 sec in block)
dir - (0.86 sec in block)DV-CPU-RV
dir block - (0.62 sec in block)
sh - (0.39 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s rv_core core/rtl/rv_alu.v core/rtl/rv_alu_ctrl.v core/rtl/rv_branch_predict.v core/rtl/rv_branch_test.v core/rtl/rv_core.v core/rtl/rv_ctrl.v core/rtl/rv_data_mem.v core/rtl/rv_div.v core/rtl/rv_dpram.v core/rtl/rv_forward.v core/rtl/rv_hzd_detect.v core/rtl/rv_imm_gen.v core/rtl/rv_instr_mem.v core/rtl/rv_mem_map.v core/rtl/rv_mul.v core/rtl/rv_rf.v
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.81 sec in block)DV-CPU-RV
dir block - (0.59 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (34 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (33 sec in block)
parallel - (33 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (32 sec in block)
stage - (32 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (32 sec in block)
lock - (31 sec in block)digilent_arty_a7_100t
lock block - (30 sec in block)
stage - (28 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (28 sec in block)
dir - (27 sec in block)DV-CPU-RV
dir block - (27 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p DV-CPU-RV -b digilent_arty_a7_100t
stage - (0.97 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.67 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.35 sec in block)
getContext - (0.16 sec in self)
stage - (0.74 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.49 sec in block)
junit - (0.25 sec in self)**/*.xml