Console Output

+ /eda/oss-cad-suite/bin/yosys -p                          read_verilog dv-cpu-rv/core/rtl/*.v;                         synth -abc9 -top rv_core                     

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+8 (git sha1 fb4cbfa73, clang 10.0.0-4ubuntu1 -fPIC -Os)


-- Running command `                         read_verilog dv-cpu-rv/core/rtl/*.v;                         synth -abc9 -top rv_core                     ' --

1. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_alu.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_alu.v' to AST representation.
Generating RTLIL representation for module `\rv_alu'.
Note: Assuming pure combinatorial block at dv-cpu-rv/core/rtl/rv_alu.v:32.1-46.4 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_alu_ctrl.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_alu_ctrl.v' to AST representation.
Generating RTLIL representation for module `\rv_alu_ctrl'.
Note: Assuming pure combinatorial block at dv-cpu-rv/core/rtl/rv_alu_ctrl.v:27.1-94.4 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_branch_predict.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_branch_predict.v' to AST representation.
Generating RTLIL representation for module `\rv_branch_predict'.
Warning: Replacing memory \bpb with list of registers. See dv-cpu-rv/core/rtl/rv_branch_predict.v:44
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_branch_test.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_branch_test.v' to AST representation.
Generating RTLIL representation for module `\rv_branch_test'.
Note: Assuming pure combinatorial block at dv-cpu-rv/core/rtl/rv_branch_test.v:30.1-40.4 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_core.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_core.v' to AST representation.
Generating RTLIL representation for module `\rv_core'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_ctrl.v
dv-cpu-rv/core/rtl/rv_ctrl.v:35: ERROR: Found non-synthesizable event list!