Console Output

+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s dependencies/blocks/src/main/resources/BlackBoxDelayBuffer.v dependencies/blocks/vsrc/SRLatch.v dependencies/constellation/src/main/resources/vsrc/TrafficEval.v dependencies/rocket-chip/src/main/resources/vsrc/AsyncResetReg.v dependencies/rocket-chip/src/main/resources/vsrc/ClockDivider2.v dependencies/rocket-chip/src/main/resources/vsrc/ClockDivider3.v dependencies/rocket-chip/src/main/resources/vsrc/EICG_wrapper.v dependencies/rocket-chip/src/main/resources/vsrc/RoccBlackBox.v dependencies/rocket-chip/src/main/resources/vsrc/SimDTM.v dependencies/rocket-chip/src/main/resources/vsrc/SimJTAG.v dependencies/rocket-chip/src/main/resources/vsrc/debug_rob.v dependencies/rocket-chip/src/main/resources/vsrc/plusarg_reader.v dependencies/rocket-chip/hardfloat/hardfloat/tests/resources/vsrc/emulator.v dependencies/rocket-chip/src/main/resources/vsrc/TestDriver.v tb/debugger/SimTop.v tb/verilator/SimLink.v tb/verilator/SimTop.v tb/verilator/test.v tb/verilator/mdl_test/Reservation_top.v tb/verilator/mdl_test/random_csr_req.v tb/verilator/mdl_test/random_op_rsl.v tb/verilator/mdl_test/random_wb_ack.v tb/vtb/SimJTAG.v tb/vtb/axi_full_slv_sram.v tb/vtb/debuger.v tb/vtb/gen_asymmetricFIFO.v tb/vtb/gen_bypassfifo.v tb/vtb/gen_counter.v tb/vtb/gen_csrreg.v tb/vtb/gen_dffr.v tb/vtb/gen_dffren.v tb/vtb/gen_dpdffren.v tb/vtb/gen_fifo.v tb/vtb/gen_ppbuff.v tb/vtb/gen_rsffr.v tb/vtb/gen_slffr.v tb/vtb/gen_sram.v tb/vtb/gen_suffr.v tb/vtb/gen_syn.v tb/vtb/lfsr.v tb/vtb/lzp.v tb/vtb/tl_mem.v
dependencies/rocket-chip/hardfloat/hardfloat/tests/resources/vsrc/emulator.v:8: warning: macro EXPERIMENT undefined (and assumed null) at this point.
dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:1: syntax error
I give up.
Segmentation fault (core dumped)