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+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p Rift2Core -b digilent_arty_a7_100t
Final configuration file generated at /var/jenkins_home/workspace/Rift2Core/Rift2Core/build_digilent_arty_a7_100t.tcl
Error executing Makefile.
ERROR: [Synth 8-2716] syntax error near '"DPI-C' [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:1]
ERROR: [Synth 8-11074] parameter initial value cannot be omitted in this mode of Verilog [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:30]
ERROR: [Synth 8-11074] parameter initial value cannot be omitted in this mode of Verilog [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:31]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:46]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:47]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:48]
ERROR: [Synth 8-8896] 'longint' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:49]
ERROR: [Synth 8-8896] 'longint' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:50]
ERROR: [Synth 8-11074] parameter initial value cannot be omitted in this mode of Verilog [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:91]
ERROR: [Synth 8-11074] parameter initial value cannot be omitted in this mode of Verilog [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:92]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:108]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:114]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/Rift2Core/Rift2Core/dependencies/constellation/src/main/resources/vsrc/TrafficEval.v:115]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/Rift2Core.v:48]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/Rift2Core.v:1]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 218, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.