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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/RiftCore
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf RiftCore
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/whutddk/RiftCore RiftCore
Cloning into 'RiftCore'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/RiftCore/RiftCore
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RiftChip/riftChip.v RiftChip/SoC/Xbar_wrap.v RiftChip/SoC/axi_ccm.v RiftChip/SoC/axi_full_slv_sram.v RiftChip/SoC/fxbar_wrap.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_addr_arbiter_sasd.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_addr_decoder.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_axi_crossbar.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_crossbar_sasd.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_decerr_slave.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_22_splitter.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_crossbar_v2_1_vl_rfs.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_data_fifo_v2_1_vl_rfs.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_full_crossbar.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_infrastructure_v1_1_vl_rfs.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_register_slice_v2_1_21_axic_register_slice.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/axi_register_slice_v2_1_vl_rfs.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/generic_baseblocks_v2_1_0_carry_and.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/generic_baseblocks_v2_1_0_comparator_static.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/generic_baseblocks_v2_1_0_mux_enc.v RiftChip/SoC/xilinx_IP/axi_full_Xbar/generic_baseblocks_v2_1_vl_rfs.v RiftChip/axi/axi_full_mst.v RiftChip/axi/axi_full_slv.v RiftChip/axi/axi_lite_mst.v RiftChip/axi/axi_lite_slv.v RiftChip/axi/AXI BUS TEMPLE/axi4_full_master.v RiftChip/axi/AXI BUS TEMPLE/axi4_full_slave.v RiftChip/axi/AXI BUS TEMPLE/axi4_lite_master.v RiftChip/axi/AXI BUS TEMPLE/axi4_lite_slave.v RiftChip/debug/DM.v RiftChip/debug/DMI.v RiftChip/debug/DTM.v RiftChip/debug/core_monitor.v RiftChip/element/gen_asymmetricFIFO.v RiftChip/element/gen_bypassfifo.v RiftChip/element/gen_counter.v RiftChip/element/gen_csrreg.v RiftChip/element/gen_dffr.v RiftChip/element/gen_dffren.v RiftChip/element/gen_dpdffren.v RiftChip/element/gen_fifo.v RiftChip/element/gen_ppbuff.v RiftChip/element/gen_ringStack.v RiftChip/element/gen_rsffr.v RiftChip/element/gen_slffr.v RiftChip/element/gen_sram.v RiftChip/element/gen_suffr.v RiftChip/element/gen_syn.v RiftChip/element/lfsr.v RiftChip/element/lzp.v RiftChip/riftCore/backEnd.v RiftChip/riftCore/frontEnd.v RiftChip/riftCore/instr_fifo.v RiftChip/riftCore/riftCore.v RiftChip/riftCore/backend/commit.v RiftChip/riftCore/backend/csrFiles.v RiftChip/riftCore/backend/dispatch.v RiftChip/riftCore/backend/phyRegister.v RiftChip/riftCore/backend/regFiles.v RiftChip/riftCore/backend/rename.v RiftChip/riftCore/backend/writeBack.v RiftChip/riftCore/backend/execute/alu.v RiftChip/riftCore/backend/execute/bru.v RiftChip/riftCore/backend/execute/csr.v RiftChip/riftCore/backend/execute/lsu.v RiftChip/riftCore/backend/execute/mul.v RiftChip/riftCore/backend/issue/alu_issue.v RiftChip/riftCore/backend/issue/bru_issue.v RiftChip/riftCore/backend/issue/csr_issue.v RiftChip/riftCore/backend/issue/issue_buffer.v RiftChip/riftCore/backend/issue/issue_fifo.v RiftChip/riftCore/backend/issue/lsu_issue.v RiftChip/riftCore/backend/issue/mul_issue.v RiftChip/riftCore/cache/L2cache.v RiftChip/riftCore/cache/L3cache.v RiftChip/riftCore/cache/cache.v RiftChip/riftCore/cache/cache_mem.v RiftChip/riftCore/cache/dirty_block.v RiftChip/riftCore/cache/wt_block.v RiftChip/riftCore/frontend/branch_predict.v RiftChip/riftCore/frontend/decoder.v RiftChip/riftCore/frontend/decoder16.v RiftChip/riftCore/frontend/decoder32.v RiftChip/riftCore/frontend/iAlign.v RiftChip/riftCore/frontend/icache.v RiftChip/riftCore/frontend/iqueue.v RiftChip/riftCore/frontend/pcGenerate.v RiftChip/riftCore/frontend/preDecode.v tb/debuger.v tb/riftChip_CI.v tb/riftChip_DS.v tb/riftChip_TB.v tb/module_test/axi_ccm_tb.v tb/module_test/axi_full_cache_tb.v tb/module_test/axi_full_l2l3c_tb.v tb/module_test/axi_full_l3c_tb.v tb/module_test/corssbar_tb.v tb/module_test/dcache_tb.v tb/module_test/div_tb.v tb/module_test/icache_tb.v tb/module_test/mem_access_tb.v
RiftChip/SoC/axi_full_slv_sram.v:33: Include file define.vh not found
Preprocessor failed with 1 errors.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
Stage "Utilities" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] stage
[Pipeline] { (Test digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 6b6716f8-cfa2-4612-bd7f-bbff0f08ad17
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE