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Start of Pipeline - (7 min 0 sec in block)
node - (6 min 55 sec in block)
node block - (6 min 51 sec in block)
stage - (10 sec in block)Git Clone
stage block (Git Clone) - (9.1 sec in block)
sh - (3.3 sec in self)rm -rf *.xml
sh - (0.92 sec in self)rm -rf SuperScalar-RISCV-CPU
sh - (2.2 sec in self)git clone --recursive --depth=1 https://github.com/risclite/SuperScalar-RISCV-CPU SuperScalar-RISCV-CPU
stage - (2.6 sec in block)Simulation
stage block (Simulation) - (1.7 sec in block)
dir - (1 sec in block)SuperScalar-RISCV-CPU
dir block - (0.58 sec in block)
echo - (0.2 sec in self)FPGA > Simulation
stage - (2.9 sec in block)Utilities
stage block (Utilities) - (2 sec in block)
dir - (1.3 sec in block)SuperScalar-RISCV-CPU
dir block - (0.91 sec in block)
sh - (0.54 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (6 min 32 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (6 min 31 sec in block)
parallel - (6 min 30 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (6 min 30 sec in block)
stage - (6 min 29 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (6 min 28 sec in block)
lock - (6 min 27 sec in block)digilent_arty_a7_100t
lock block - (6 min 26 sec in block)
stage - (6 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (6 min 22 sec in block)
dir - (6 min 22 sec in block)SuperScalar-RISCV-CPU
dir block - (6 min 22 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (6 min 21 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p SuperScalar-RISCV-CPU -b digilent_arty_a7_100t
stage - (2.1 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (1.5 sec in block)
dir - (1.1 sec in block)SuperScalar-RISCV-CPU
dir block - (0.81 sec in block)
echo - (0.15 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (0.44 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p SuperScalar-RISCV-CPU -b digilent_arty_a7_100t -l
stage - (0.6 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (0.33 sec in block)
getContext - (0.15 sec in self)
stage - (0.71 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.48 sec in block)
junit - (0.23 sec in self)**/*.xml