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Start of Pipeline - (4 min 27 sec in block)
node - (4 min 25 sec in block)
node block - (4 min 24 sec in block)
stage - (6.2 sec in block)Git Clone
stage block (Git Clone) - (4.1 sec in block)
sh - (0.9 sec in self)rm -rf *.xml
sh - (1.3 sec in self)rm -rf T03x
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/klessydra/T03x T03x
stage - (4.6 sec in block)Simulation
stage block (Simulation) - (3.1 sec in block)
dir - (1.9 sec in block)T03x
dir block - (1.1 sec in block)
echo - (0.36 sec in self)FPGA > Simulation
stage - (5.2 sec in block)Utilities
stage block (Utilities) - (3.7 sec in block)
dir - (2.4 sec in block)T03x
dir block - (1.6 sec in block)
sh - (0.77 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (4 min 6 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (4 min 5 sec in block)
parallel - (4 min 4 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (4 min 3 sec in block)
stage - (4 min 1 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (4 min 0 sec in block)
lock - (3 min 58 sec in block)digilent_arty_a7_100t
lock block - (3 min 55 sec in block)
stage - (3 min 40 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3 min 40 sec in block)
dir - (3 min 38 sec in block)T03x
dir block - (3 min 38 sec in block)
echo - (0.64 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (3 min 36 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p T03x -b digilent_arty_a7_100t
stage - (5.8 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (4.9 sec in block)
dir - (4.4 sec in block)T03x
dir block - (4 sec in block)
echo - (0.16 sec in self)Flashing FPGA digilent_arty_a7_100t.
sh - (3.7 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p T03x -b digilent_arty_a7_100t -l
stage - (7.9 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (7.4 sec in block)
echo - (0.26 sec in self)Testing FPGA digilent_arty_a7_100t.
sh - (0.77 sec in self)echo "Test for FPGA in /dev/ttyUSB1"
sh - (5.9 sec in self)python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm
stage - (0.84 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.6 sec in block)
junit - (0.35 sec in self)**/*.xml