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Start of Pipeline - (48 sec in block)
node - (47 sec in block)
node block - (46 sec in block)
stage - (15 sec in block)Git Clone
stage block (Git Clone) - (13 sec in block)
sh - (0.67 sec in self)rm -rf *.xml
sh - (3.1 sec in self)rm -rf VexRiscv
sh - (9.7 sec in self)git clone --recursive --depth=1 https://github.com/SpinalHDL/VexRiscv VexRiscv
stage - (7.6 sec in block)Verilog Convert
stage block (Verilog Convert) - (5.2 sec in block)
dir - (3.1 sec in block)VexRiscv
dir block - (2 sec in block)
sh - (1.2 sec in self)sbt "runMain vexriscv.demo.GenFull"
stage - (3.6 sec in block)Simulation
stage block (Simulation) - (1.5 sec in block)
getContext - (0.67 sec in self)
stage - (4.3 sec in block)Utilities
stage block (Utilities) - (1.8 sec in block)
getContext - (1 sec in self)
stage - (13 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (12 sec in block)
getContext - (0.78 sec in self)
parallel - (11 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (10 sec in block)
stage - (9.3 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (8.6 sec in block)
getContext - (0.84 sec in self)
stage - (2.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (0.82 sec in block)
getContext - (0.37 sec in self)
stage - (2.5 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (0.85 sec in block)
getContext - (0.38 sec in self)
stage - (2.2 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.1 sec in block)
getContext - (0.41 sec in self)
stage - (1.2 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.56 sec in block)
junit - (0.28 sec in self)**/*.xml