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Start of Pipeline - (5 min 33 sec in block)
node - (5 min 32 sec in block)
node block - (5 min 32 sec in block)
stage - (3.1 sec in block)Git Clone
stage block (Git Clone) - (2.6 sec in block)
sh - (0.47 sec in self)rm -rf *.xml
sh - (0.67 sec in self)rm -rf biriscv
sh - (1.2 sec in self)git clone --recursive --depth=1 https://github.com/ultraembedded/biriscv biriscv
stage - (1.4 sec in block)Simulation
stage block (Simulation) - (0.98 sec in block)
dir - (0.62 sec in block)biriscv
dir block - (0.33 sec in block)
echo - (0.11 sec in self)FPGA > Simulation
stage - (1.7 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.87 sec in block)biriscv
dir block - (0.61 sec in block)
sh - (0.41 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (5 min 25 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (5 min 25 sec in block)
parallel - (5 min 25 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (5 min 25 sec in block)
stage - (5 min 24 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (5 min 24 sec in block)
lock - (5 min 24 sec in block)digilent_arty_a7_100t
lock block - (5 min 24 sec in block)
stage - (5 min 23 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (5 min 23 sec in block)
dir - (5 min 23 sec in block)biriscv
dir block - (5 min 23 sec in block)
echo - (0.17 sec in self)Starting synthesis for FPGA digilent_arty_a7_100t.
sh - (5 min 23 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p biriscv -b digilent_arty_a7_100t