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Start of Pipeline - (6 min 44 sec in block)
node - (6 min 42 sec in block)
node block - (1 min 45 sec in block)
stage - (51 sec in block)Git Clone
stage block (Git Clone) - (49 sec in block)
sh - (0.79 sec in self)rm -rf *.xml
sh - (1.6 sec in self)rm -rf cva6
sh - (46 sec in self)git clone --recursive --depth=1 https://github.com/openhwgroup/cva6 cva6
stage - (7.8 sec in block)Simulation
stage block (Simulation) - (5 sec in block)
dir - (3 sec in block)cva6
dir block - (1.7 sec in block)
echo - (0.61 sec in self)FPGA > Simulation
stage - (10 sec in block)Utilities
stage block (Utilities) - (6.6 sec in block)
dir - (4.2 sec in block)cva6
dir block - (2.6 sec in block)
sh - (1.5 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels
stage - (31 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (28 sec in block)
getContext - (1.4 sec in self)
parallel - (25 sec in block)
parallel block (Branch: digilent_arty_a7_100t) - (23 sec in block)
stage - (20 sec in block)digilent_arty_a7_100t
stage block (digilent_arty_a7_100t) - (19 sec in block)
getContext - (1.7 sec in self)
stage - (6.1 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1.7 sec in block)
getContext - (0.71 sec in self)
stage - (5.2 sec in block)Flash digilent_arty_a7_100t
stage block (Flash digilent_arty_a7_100t) - (2 sec in block)
getContext - (0.76 sec in self)
stage - (3.1 sec in block)Test digilent_arty_a7_100t
stage block (Test digilent_arty_a7_100t) - (1.7 sec in block)
getContext - (0.78 sec in self)
stage - (3.5 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (2.4 sec in block)
junit - (1.2 sec in self)**/*.xml