Console Output

+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p ibex -b digilent_arty_a7_100t
[LOCK] Criado: run.lock
File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'.
Final configuration file generated at /var/jenkins_home/workspace/ibex/ibex/build_digilent_arty_a7_100t.tcl
[LOCK] Removido: run.lock
Error executing Makefile.
ERROR: [Synth 8-36] 'ibex_cheriot_pkg' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:13]
ERROR: [Synth 8-36] 'cap_t' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:66]
ERROR: [Synth 8-36] 'cheriot_csr_op_e' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:67]
ERROR: [Synth 8-36] 'cap_t' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:73]
ERROR: [Synth 8-36] 'decoded_cap_t' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:155]
ERROR: [Synth 8-36] 'decoded_cap_t' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:156]
ERROR: [Synth 8-36] 'CHERIOT_SCR_DEPCC' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2015]
ERROR: [Synth 8-36] 'NULL_CAP' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2018]
ERROR: [Synth 8-36] 'CHERIOT_SCR_DSCRATCHC0' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2020]
ERROR: [Synth 8-36] 'NULL_CAP' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2023]
ERROR: [Synth 8-36] 'CHERIOT_SCR_DSCRATCHC1' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2025]
ERROR: [Synth 8-36] 'NULL_CAP' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2028]
ERROR: [Synth 8-36] 'CHERIOT_SCR_MTCC' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2030]
ERROR: [Synth 8-36] 'CHERIOT_SCR_MTDC' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2035]
ERROR: [Synth 8-36] 'CHERIOT_SCR_MSCRATCHC' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2040]
ERROR: [Synth 8-36] 'CHERIOT_SCR_MEPCC' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2045]
ERROR: [Synth 8-36] 'NULL_CAP' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2053]
ERROR: [Synth 8-36] 'ROOT_DECODED_CAP_TX' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2064]
ERROR: [Synth 8-36] 'NULL_CAP' is not declared [/var/jenkins_home/workspace/ibex/ibex/rtl/ibex_cs_registers.sv:2090]
ERROR: [Synth 8-439] module 'fpga_top' not found
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 142, in <module>
    main(
  File "/eda/processor_ci/main.py", line 89, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 299, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.