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WARNING: [Synth 8-7129] Port write_data[27] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[15] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[14] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[13] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[12] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[11] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[10] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[9] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[8] in module GPIOS is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[16] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[15] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[14] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[13] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[12] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[11] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[10] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[9] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[8] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[7] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[6] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[5] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[1] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[31] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[30] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[29] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[28] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[27] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[26] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[25] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[24] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[23] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[22] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[21] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[20] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[19] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[18] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[17] in module UART is either unconnected or has no load
WARNING: [Synth 8-7129] Port write_data[16] in module UART is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.785 ; gain = 489.684 ; free physical = 9035 ; free virtual = 28857
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.598 ; gain = 507.496 ; free physical = 9037 ; free virtual = 28859
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2131.598 ; gain = 507.496 ; free physical = 9037 ; free virtual = 28859
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2131.598 ; gain = 0.000 ; free physical = 9037 ; free virtual = 28859
Info: at iteration #5: temp = 0.000000, timing cost = 4484, wirelen = 23904
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2280.348 ; gain = 0.000 ; free physical = 9020 ; free virtual = 28841
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2280.383 ; gain = 0.000 ; free physical = 9013 ; free virtual = 28834
Info: at iteration #10: temp = 0.000000, timing cost = 4682, wirelen = 22935
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9006 ; free virtual = 28828
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9006 ; free virtual = 28828
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9006 ; free virtual = 28828
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'Control_Unit'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tool_tx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 0000000000000001 | 0000
DECODE | 0000000000000010 | 0001
MEMADR | 0000000000000100 | 0010
MEMREAD | 0000000000001000 | 0011
MEMWB | 0000000000010000 | 0100
MEMWRITE | 0000000000100000 | 0101
EXECUTER | 0000000001000000 | 0110
EXECUTEI | 0000000010000000 | 1000
JAL | 0000000100000000 | 1001
BEQ | 0000001000000000 | 1010
AUIPC | 0000010000000000 | 1100
LUI | 0000100000000000 | 1101
JALR_PC | 0001000000000000 | 1110
JALR | 0010000000000000 | 1011
ALUWB | 0100000000000000 | 0111
EXECUTECSR | 1000000000000000 | 1111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 9002 ; free virtual = 28825
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 44
16 Bit Registers := 2
11 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 17
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
3 Input 33 Bit Muxes := 1
4 Input 32 Bit Muxes := 18
2 Input 32 Bit Muxes := 36
8 Input 32 Bit Muxes := 1
16 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
16 Input 16 Bit Muxes := 1
11 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
8 Input 4 Bit Muxes := 1
23 Input 4 Bit Muxes := 1
10 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 14
16 Input 2 Bit Muxes := 3
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 49
16 Input 1 Bit Muxes := 6
4 Input 1 Bit Muxes := 2
13 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
[80%] Tech-Mapping Phase 3 completed
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":172)
WARN (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Info: at iteration #15: temp = 0.000000, timing cost = 4741, wirelen = 22302
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #20: temp = 0.000000, timing cost = 4374, wirelen = 22072
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
Info: at iteration #25: temp = 0.000000, timing cost = 3684, wirelen = 21996
Info: at iteration #27: temp = 0.000000, timing cost = 3720, wirelen = 22001
Info: SA placement time 21.67s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 39.09 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 9.43 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.36 ns
Info: Slack histogram:
Info: legend: * represents 44 endpoint(s)
Info: + represents [1,44) endpoint(s)
Info: [ 14421, 15662) |+
Info: [ 15662, 16903) |+
Info: [ 16903, 18144) |**+
Info: [ 18144, 19385) |******+
Info: [ 19385, 20626) |****+
Info: [ 20626, 21867) |***+
Info: [ 21867, 23108) |**+
Info: [ 23108, 24349) |****+
Info: [ 24349, 25590) |******************+
Info: [ 25590, 26831) |********************************+
Info: [ 26831, 28072) |************************************************************
Info: [ 28072, 29313) |****************************+
Info: [ 29313, 30554) |********+
Info: [ 30554, 31795) |*+
Info: [ 31795, 33036) |+
Info: [ 33036, 34277) |**+
Info: [ 34277, 35518) |******+
Info: [ 35518, 36759) |******+
Info: [ 36759, 38000) |*****+
Info: [ 38000, 39241) |**+
Info: Checksum: 0x7f300386
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 28866 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 156 843 | 156 843 | 28076| 0.62 0.62|
Info: 2000 | 293 1706 | 137 863 | 27463| 0.27 0.89|
Info: 3000 | 410 2589 | 117 883 | 26810| 0.28 1.18|
Info: 4000 | 541 3458 | 131 869 | 26023| 0.26 1.44|
Info: 5000 | 683 4316 | 142 858 | 25401| 0.26 1.70|
Info: 6000 | 764 5235 | 81 919 | 25148| 0.27 1.96|
Info: 7000 | 981 6018 | 217 783 | 24587| 0.23 2.20|
Info: 8000 | 1115 6884 | 134 866 | 24220| 0.23 2.42|
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8824 ; free virtual = 28656
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Info: 9000 | 1311 7688 | 196 804 | 23535| 0.26 2.68|
Info: 10000 | 1509 8490 | 198 802 | 22788| 0.24 2.92|
Info: 11000 | 1717 9282 | 208 792 | 22149| 0.25 3.17|
Info: 12000 | 1951 10048 | 234 766 | 21445| 0.25 3.42|
Info: 13000 | 2090 10909 | 139 861 | 21145| 0.25 3.67|
Info: 14000 | 2246 11753 | 156 844 | 20645| 0.28 3.95|
Info: 15000 | 2480 12519 | 234 766 | 19951| 0.28 4.23|
Info: 16000 | 2635 13364 | 155 845 | 19367| 0.28 4.51|
Info: 17000 | 2844 14155 | 209 791 | 18853| 0.30 4.81|
Info: 18000 | 3078 14921 | 234 766 | 18470| 0.37 5.18|
Info: 19000 | 3331 15668 | 253 747 | 17824| 0.28 5.46|
Info: 20000 | 3614 16385 | 283 717 | 17320| 0.30 5.76|
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8815 ; free virtual = 28647
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: 21000 | 3926 17073 | 312 688 | 16836| 0.31 6.07|
Info: 22000 | 4240 17759 | 314 686 | 16273| 0.32 6.38|
Info: 23000 | 4574 18425 | 334 666 | 15727| 0.34 6.73|
Info: 24000 | 4931 19068 | 357 643 | 15192| 0.33 7.06|
Info: 25000 | 5312 19687 | 381 619 | 14761| 0.33 7.39|
Info: 26000 | 5628 20371 | 316 684 | 14163| 0.31 7.70|
Info: 27000 | 6016 20983 | 388 612 | 13675| 0.33 8.03|
Info: 28000 | 6387 21612 | 371 629 | 13159| 0.30 8.33|
Info: 29000 | 6819 22180 | 432 568 | 12732| 0.33 8.66|
Info: 30000 | 7265 22734 | 446 554 | 12282| 0.33 8.99|
Info: 31000 | 7664 23335 | 399 601 | 11936| 0.33 9.33|
Info: 32000 | 8097 23902 | 433 567 | 11474| 0.33 9.66|
[30%] Placement Phase 2 completed
Info: 33000 | 8494 24483 | 397 581 | 10957| 0.32 9.98|
Info: 34000 | 8902 24990 | 408 507 | 10465| 0.29 10.27|
Info: 35000 | 9145 25575 | 243 585 | 9745| 0.21 10.47|
Info: 36000 | 9523 26090 | 378 515 | 9240| 0.29 10.76|
Info: 37000 | 9880 26621 | 357 531 | 8696| 0.27 11.03|
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8813 ; free virtual = 28645
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
Info: 38000 | 10158 27257 | 278 636 | 8000| 0.20 11.24|
Info: 39000 | 10473 27871 | 315 614 | 7540| 0.28 11.51|
Info: 40000 | 10768 28477 | 295 606 | 6899| 0.25 11.76|
Info: 41000 | 11111 29085 | 343 608 | 6262| 0.30 12.06|
Info: 42000 | 11357 29807 | 246 722 | 5596| 0.32 12.38|
Info: 43000 | 11399 30752 | 42 945 | 4691| 0.12 12.50|
Info: 44000 | 11431 31697 | 32 945 | 3723| 0.08 12.58|
Info: 45000 | 11454 32671 | 23 974 | 2748| 0.08 12.66|
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8733 ; free virtual = 28565
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
Info: 46000 | 11636 33482 | 182 811 | 1959| 0.24 12.90|
Info: 47000 | 11752 34250 | 116 768 | 1085| 0.28 13.18|
Info: 48000 | 11791 34933 | 39 683 | 148| 0.22 13.40|
Info: 48147 | 11791 35013 | 0 80 | 0| 0.08 13.49|
Info: Routing complete.
Info: Router1 time 13.49s
Info: Checksum: 0xab8aa729
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q.Q
Info: 1.5 2.0 Net SOC.Core.Control_Unit.nextstate_PFUMX_Z_2_C0[0] (19,21) -> (21,25)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.A
Info: Defined in:
Info: Risco-5/src/core/control_unit.v:51.11-51.16
Info: 0.2 2.3 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: 1.4 3.6 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (21,25) -> (21,14)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 3.9 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1_LUT4_Z.F
Info: 1.8 5.7 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B1 (21,14) -> (21,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.B
Info: 0.4 6.1 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.1 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,26) -> (21,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,26) -> (21,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,26) -> (21,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (21,26) -> (21,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.2 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.2 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (21,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.3 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.3 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.4 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.4 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.5 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.5 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (22,26) -> (22,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.5 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.5 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (22,26) -> (23,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.6 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.6 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (23,26) -> (23,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.6 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.6 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (23,26) -> (23,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.7 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.7 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (23,26) -> (23,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.7 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.7 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B0_COUT (23,26) -> (23,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.7 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.7 Net SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_FCI_INT (23,26) -> (23,26)
Info: Sink SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.7 Source SOC.GPIOS.write_data_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_B0_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.7 Net $nextpnr_CCU2C_29$CIN (23,26) -> (23,26)
Info: Sink $nextpnr_CCU2C_29$CCU2_COMB0.FCI
Info: 0.4 7.2 Source $nextpnr_CCU2C_29$CCU2_COMB0.F
Info: 1.4 8.6 Net SOC.Bus.slave_1_write_LUT4_Z_C[3] (23,26) -> (13,29)
Info: Sink SOC.Memory.address_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 8.8 Source SOC.Memory.address_LUT4_Z.F
Info: 1.9 10.7 Net SOC.slave_address[5] (13,29) -> (3,32)
Info: Sink SOC.Memory.memory.0.121$DPRAM_COMB3.A
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.5-22.18
Info: 0.2 10.9 Source SOC.Memory.memory.0.121$DPRAM_COMB3.F
Info: 0.6 11.6 Net SOC.Memory.memory.0.97_DO[2] (3,32) -> (4,32)
Info: Sink SOC.Memory.memory.0.97_DO_LUT4_C.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 11.8 Source SOC.Memory.memory.0.97_DO_LUT4_C.F
Info: 0.9 12.7 Net SOC.Memory.memory.0.97_DO_LUT4_C_Z[0] (4,32) -> (4,33)
Info: Sink SOC.Memory.memory.0.41_DO_LUT4_C_Z_LUT4_Z.B
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.9 Source SOC.Memory.memory.0.41_DO_LUT4_C_Z_LUT4_Z.F
Info: 0.7 13.6 Net SOC.Memory.memory.0.41_DO_LUT4_C_Z[3] (4,33) -> (3,33)
Info: Sink SOC.Memory.memory.0.73_DO_LUT4_C_Z_LUT4_Z_1.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 13.8 Source SOC.Memory.memory.0.73_DO_LUT4_C_Z_LUT4_Z_1.F
Info: 0.7 14.6 Net SOC.Memory.memory.0.73_DO_LUT4_C_Z[4] (3,33) -> (3,31)
Info: Sink SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 14.8 Source SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.7 15.5 Net SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z[3] (3,31) -> (5,30)
Info: Sink SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_LUT4_B.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 15.7 Source SOC.Memory.memory.0.9_DO_LUT4_C_Z_LUT4_A_Z_LUT4_B.F
Info: 1.6 17.4 Net SOC.Core.read_data_LUT4_Z_7_C[3] (5,30) -> (19,26)
Info: Sink SOC.Memory.memory.0.175_DO_PFUMX_C0_Z_LUT4_C_Z_PFUMX_C0_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 17.6 Source SOC.Memory.memory.0.175_DO_PFUMX_C0_Z_LUT4_C_Z_PFUMX_C0_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 1.3 19.0 Net SOC.Core.read_data_PFUMX_Z_10_BLUT_LUT4_Z_D[4] (19,26) -> (24,33)
Info: Sink SOC.Core.read_data_PFUMX_Z_8_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 19.2 Source SOC.Core.read_data_PFUMX_Z_8_BLUT_LUT4_Z.OFX
Info: 1.6 20.8 Net SOC.read_data[24] (24,33) -> (17,23)
Info: Sink SOC.Core.instruction_register_TRELLIS_FF_Q_7.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 20.8 Setup SOC.Core.instruction_register_TRELLIS_FF_Q_7.M
Info: 4.7 ns logic, 16.1 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source gpios[2]$tr_io.O
Info: 4.7 4.7 Net gpios[2]$TRELLIS_IO_IN (90,23) -> (14,23)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_C.B
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:7.16-7.21
Info: 0.2 4.9 Source SOC.GPIOS.Gpios[2].direction_LUT4_C.F
Info: 0.6 5.5 Net SOC.GPIOS.Gpios[2].direction_LUT4_C_Z[2] (14,23) -> (14,23)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_1_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 5.8 Source SOC.Uart.RX_FIFO.memory.0.0_DO_1_LUT4_Z.F
Info: 1.0 6.8 Net SOC.Uart.RX_FIFO.memory.0.0_DO_1[3] (14,23) -> (15,19)
Info: Sink SOC.Core.read_data_LUT4_Z_2.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 7.0 Source SOC.Core.read_data_LUT4_Z_2.F
Info: 0.4 7.4 Net SOC.read_data[2] (15,19) -> (15,19)
Info: Sink SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 7.4 Setup SOC.Core.memory_register_TRELLIS_FF_Q_29.M
Info: 0.7 ns logic, 6.7 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.GPIOS.Gpios[2].direction_TRELLIS_FF_Q.Q
Info: 4.0 4.6 Net SOC.GPIOS.gpio_direction[2] (13,23) -> (74,23)
Info: Sink SOC.GPIOS.Gpios[2].direction_LUT4_D.D
Info: Defined in:
Info: Risco-5/src/peripheral/gpios.v:14.19-14.33
Info: 0.2 4.8 Source SOC.GPIOS.Gpios[2].direction_LUT4_D.F
Info: 1.0 5.8 Net gpios_$_TBUF__Y_3_E (74,23) -> (83,23)
Info: Sink gpios[2]$tr_io$invert_T.A
Info: 0.2 6.0 Source gpios[2]$tr_io$invert_T.F
Info: 1.3 7.3 Net gpios[2]$tr_io$invert_T$conn$Z (83,23) -> (90,23)
Info: Sink gpios[2]$tr_io.T
Info: 1.0 ns logic, 6.3 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 48.00 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.42 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.27 ns
Info: Slack histogram:
Info: legend: * represents 50 endpoint(s)
Info: + represents [1,50) endpoint(s)
Info: [ 19168, 20163) |+
Info: [ 20163, 21158) |+
Info: [ 21158, 22153) |******+
Info: [ 22153, 23148) |*****+
Info: [ 23148, 24143) |*+
Info: [ 24143, 25138) |*+
Info: [ 25138, 26133) |***+
Info: [ 26133, 27128) |**************+
Info: [ 27128, 28123) |**********+
Info: [ 28123, 29118) |*********************************+
Info: [ 29118, 30113) |************************************************************
Info: [ 30113, 31108) |****+
Info: [ 31108, 32103) |**+
Info: [ 32103, 33098) |*******+
Info: [ 33098, 34093) |***+
Info: [ 34093, 35088) |*+
Info: [ 35088, 36083) |***+
Info: [ 36083, 37078) |******+
Info: [ 37078, 38073) |******+
Info: [ 38073, 39068) |***
Info: Program finished normally.
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
[Pipeline] // stage
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28834
---------------------------------------------------------------------------------
[Pipeline] }
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8978 ; free virtual = 28830
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8977 ; free virtual = 28829
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 55|
|3 |LUT1 | 11|
|4 |LUT2 | 150|
|5 |LUT3 | 68|
|6 |LUT4 | 140|
|7 |LUT5 | 380|
|8 |LUT6 | 1376|
|9 |MUXF7 | 256|
|10 |RAM256X1S | 64|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDRE | 1739|
|14 |FDSE | 5|
|15 |LD | 4|
|16 |IBUF | 2|
|17 |IOBUF | 8|
|18 |OBUF | 9|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8983 ; free virtual = 28835
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 43 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2280.383 ; gain = 507.496 ; free physical = 8982 ; free virtual = 28833
Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2280.383 ; gain = 656.281 ; free physical = 8982 ; free virtual = 28833
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2280.383 ; gain = 0.000 ; free physical = 9256 ; free virtual = 29108
INFO: [Netlist 29-17] Analyzing 393 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2352.379 ; gain = 0.000 ; free physical = 9255 ; free virtual = 29107
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 82 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 8 instances
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 5bd2eccb
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2352.414 ; gain = 1035.320 ; free physical = 9255 ; free virtual = 29106
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2054.456; main = 1778.755; forked = 422.401
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3225.988; main = 2352.383; forked = 969.652
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2416.410 ; gain = 63.996 ; free physical = 9254 ; free virtual = 29106
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: c8f6debf
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2519.238 ; gain = 102.828 ; free physical = 9215 ; free virtual = 29067
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: c8f6debf
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: c8f6debf
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 1 Initialization | Checksum: c8f6debf
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: c8f6debf
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: c8f6debf
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 2 Timer Update And Timing Data Collection | Checksum: c8f6debf
Time (s): cpu = 00:00:00.3 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 3 inverters resulting in an inversion of 9 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 8eda6a4f
Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Retarget | Checksum: 8eda6a4f
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 8eda6a4f
Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Constant propagation | Checksum: 8eda6a4f
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 15094a4a4
Time (s): cpu = 00:00:00.47 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2770.145 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28794
Sweep | Checksum: 15094a4a4
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 15094a4a4
Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28794
BUFG optimization | Checksum: 15094a4a4
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 15094a4a4
Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28794
Shift Register Optimization | Checksum: 15094a4a4
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 905269d5
Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28794
Post Processing Netlist | Checksum: 905269d5
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: cad3eec1
Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
Phase 9.2 Verifying Netlist Connectivity | Checksum: cad3eec1
Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
Phase 9 Finalization | Checksum: cad3eec1
Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 3 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: cad3eec1
Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2802.160 ; gain = 32.016 ; free physical = 8942 ; free virtual = 28793
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
[50%] Placement Phase 3 completed
Running routing......
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: cad3eec1
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: cad3eec1
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
Ending Netlist Obfuscation Task | Checksum: cad3eec1
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2802.160 ; gain = 0.000 ; free physical = 8942 ; free virtual = 28793
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2802.160 ; gain = 449.746 ; free physical = 8942 ; free virtual = 28793
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8941 ; free virtual = 28793
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7ffa9969
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8941 ; free virtual = 28793
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8941 ; free virtual = 28793
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 851f817e
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2834.176 ; gain = 0.000 ; free physical = 8932 ; free virtual = 28784
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: ec301d64
Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8935 ; free virtual = 28787
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: ec301d64
Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8935 ; free virtual = 28787
Phase 1 Placer Initialization | Checksum: ec301d64
Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8935 ; free virtual = 28787
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: db2775b0
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8931 ; free virtual = 28783
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1580cb01c
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8929 ; free virtual = 28781
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1580cb01c
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8929 ; free virtual = 28781
Phase 2.4 Global Placement Core
[60%] Routing Phase 0 completed
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: ed4fdaab
Time (s): cpu = 00:00:26 ; elapsed = 00:00:07 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28713
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 39 LUTNM shape to break, 40 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 13, two critical 26, total 39, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 54 nets or LUTs. Breaked 39 LUTs, combined 15 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8862 ; free virtual = 28713
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 39 | 15 | 54 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 39 | 15 | 54 | 0 | 9 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 127c78cd0
Time (s): cpu = 00:00:27 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28713
Phase 2.4 Global Placement Core | Checksum: 136b43015
Time (s): cpu = 00:00:32 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28714
Phase 2 Global Placement | Checksum: 136b43015
Time (s): cpu = 00:00:32 ; elapsed = 00:00:08 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28714
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: e9b42c39
Time (s): cpu = 00:00:33 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8862 ; free virtual = 28714
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: f6e766f4
Time (s): cpu = 00:00:35 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8859 ; free virtual = 28711
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 159da352b
Time (s): cpu = 00:00:35 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8857 ; free virtual = 28709
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 13a8d2123
Time (s): cpu = 00:00:35 ; elapsed = 00:00:09 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8855 ; free virtual = 28707
Phase 3.5 Fast Optimization
Phase 3.5 Fast Optimization | Checksum: dc99ae94
Time (s): cpu = 00:00:39 ; elapsed = 00:00:11 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8852 ; free virtual = 28704
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1b604b750
Time (s): cpu = 00:00:41 ; elapsed = 00:00:13 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8861 ; free virtual = 28712
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 18ac65933
Time (s): cpu = 00:00:41 ; elapsed = 00:00:13 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8861 ; free virtual = 28712
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1b15bcf4f
Time (s): cpu = 00:00:41 ; elapsed = 00:00:13 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8861 ; free virtual = 28712
Phase 3.9 Fast Optimization
[70%] Routing Phase 1 completed
Phase 3.9 Fast Optimization | Checksum: 1a52de3d5
Time (s): cpu = 00:00:47 ; elapsed = 00:00:16 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8858 ; free virtual = 28709
Phase 3 Detail Placement | Checksum: 1a52de3d5
Time (s): cpu = 00:00:47 ; elapsed = 00:00:16 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8858 ; free virtual = 28709
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 21ff37f8e
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.027 | TNS=-40.611 |
Phase 1 Physical Synthesis Initialization | Checksum: 1c032e1c9
Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8877 ; free virtual = 28729
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1c032e1c9
Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8877 ; free virtual = 28729
Phase 4.1.1.1 BUFG Insertion | Checksum: 21ff37f8e
Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8874 ; free virtual = 28726
Phase 4.1.1.2 Post Placement Timing Optimization
[80%] Routing Phase 2 completed
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
INFO: [Place 30-746] Post Placement Timing Summary WNS=-0.176. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1a34d6670
Time (s): cpu = 00:01:16 ; elapsed = 00:00:39 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700
Time (s): cpu = 00:01:16 ; elapsed = 00:00:39 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700
Phase 4.1 Post Commit Optimization | Checksum: 1a34d6670
Time (s): cpu = 00:01:16 ; elapsed = 00:00:39 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1a34d6670
Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 8x8|
|___________|___________________|___________________|
| South| 1x1| 2x2|
|___________|___________________|___________________|
| East| 2x2| 4x4|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1a34d6670
Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
Phase 4.3 Placer Reporting | Checksum: 1a34d6670
Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8842 ; free virtual = 28700
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 8841 ; free virtual = 28699
Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8841 ; free virtual = 28699
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19ff18b3e
Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Sun Apr 14 02:07:00 2024
Ending Placer Task | Checksum: 10983f1f3
Time (s): cpu = 00:01:17 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 7.027 ; free physical = 8844 ; free virtual = 28701
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:18 ; elapsed = 00:00:40 . Memory (MB): peak = 2841.203 ; gain = 39.043 ; free physical = 8844 ; free virtual = 28701
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
[Pipeline] }
# report_io -file digilent_nexys4ddr_io.rpt
[Pipeline] // stage
[Pipeline] }
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9160 ; free virtual = 29018
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9159 ; free virtual = 29017
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 8d76f748 ConstDB: 0 ShapeSum: 7c0cfaab RouteDB: 0
Post Restoration Checksum: NetGraph: 618cf839 | NumContArr: cdc5ae4e | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2b4a49bc1
Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9153 ; free virtual = 29011
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 2b4a49bc1
Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9153 ; free virtual = 29011
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 2b4a49bc1
Time (s): cpu = 00:00:32 ; elapsed = 00:00:26 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9153 ; free virtual = 29011
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 22c5afb3d
Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9132 ; free virtual = 28991
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.183 | TNS=0.000 | WHS=-0.203 | THS=-11.695|
Router Utilization Summary
Global Vertical Routing Utilization = 0.00130565 %
Global Horizontal Routing Utilization = 0.00269963 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3402
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3399
Number of Partially Routed Nets = 3
Number of Node Overlaps = 2
Phase 2 Router Initialization | Checksum: 204d1efb4
Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 204d1efb4
Time (s): cpu = 00:00:39 ; elapsed = 00:00:28 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1c658fb38
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988
Phase 3 Initial Routing | Checksum: 1c658fb38
Time (s): cpu = 00:00:41 ; elapsed = 00:00:29 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9130 ; free virtual = 28988
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1976
Number of Nodes with overlaps = 844
Number of Nodes with overlaps = 465
Number of Nodes with overlaps = 296
Number of Nodes with overlaps = 219
Number of Nodes with overlaps = 126
Number of Nodes with overlaps = 87
Number of Nodes with overlaps = 60
Number of Nodes with overlaps = 42
Number of Nodes with overlaps = 32
Number of Nodes with overlaps = 9
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.944 | TNS=-43.454| WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 136f795a3
Time (s): cpu = 00:01:23 ; elapsed = 00:00:44 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9104 ; free virtual = 28962
Phase 4.2 Global Iteration 1
Number of Nodes with overlaps = 496
Number of Nodes with overlaps = 405
Number of Nodes with overlaps = 284
Number of Nodes with overlaps = 187
Number of Nodes with overlaps = 79
Number of Nodes with overlaps = 56
Number of Nodes with overlaps = 33
Number of Nodes with overlaps = 24
Number of Nodes with overlaps = 10
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.655 | TNS=-65.213| WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 301d176df
Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9113 ; free virtual = 28971
Phase 4 Rip-up And Reroute | Checksum: 301d176df
Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9113 ; free virtual = 28971
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 2a1f5a147
Time (s): cpu = 00:01:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9113 ; free virtual = 28972
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.930 | TNS=-40.340| WHS=N/A | THS=N/A |
Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 1c3fe5053
Time (s): cpu = 00:01:48 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9111 ; free virtual = 28970
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1c3fe5053
Time (s): cpu = 00:01:48 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9111 ; free virtual = 28970
Phase 5 Delay and Skew Optimization | Checksum: 1c3fe5053
Time (s): cpu = 00:01:48 ; elapsed = 00:00:54 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9111 ; free virtual = 28970
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2008ed711
Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.930 | TNS=-34.680| WHS=0.037 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 28b474cb6
Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Phase 6 Post Hold Fix | Checksum: 28b474cb6
Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.07116 %
Global Horizontal Routing Utilization = 1.42917 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 61.2613%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 78.3784%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 79.4118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 77.9412%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 28b474cb6
Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 28b474cb6
Time (s): cpu = 00:01:49 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 31934ba8b
Time (s): cpu = 00:01:50 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.930 | TNS=-34.680| WHS=0.037 | THS=0.000 |
WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 31934ba8b
Time (s): cpu = 00:01:51 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 10c07316a
Time (s): cpu = 00:01:51 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Ending Routing Task | Checksum: 10c07316a
Time (s): cpu = 00:01:51 ; elapsed = 00:00:55 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:52 ; elapsed = 00:00:56 . Memory (MB): peak = 2841.203 ; gain = 0.000 ; free physical = 9118 ; free virtual = 28977
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (12)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (4)
5. checking no_input_delay (9)
6. checking no_output_delay (17)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (12)
-------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[6]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[7]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (4)
------------------------------------------------
There are 4 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (9)
------------------------------
There are 9 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (17)
--------------------------------
There are 17 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-0.931 -34.505 97 6709 0.037 0.000 0 6709 3.750 0.000 0 2033
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin -0.931 -34.505 97 6709 0.037 0.000 0 6709 3.750 0.000 0 2033
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[9]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3152.492 ; gain = 229.363 ; free physical = 8771 ; free virtual = 28636
INFO: [Common 17-206] Exiting Vivado at Sun Apr 14 02:08:20 2024...
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
The resource [ecp5] is locked by build SERV #75 #75 since Apr 14, 2024, 2:08 AM.
[ecp5] is not free, waiting for execution ...
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Lock acquired on [ecp5]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
[Pipeline] echo
+ echo gravando na tang nano
gravando na tang nano
FPGA Nexys 4 Broqueada
[Pipeline] sh
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
Load SRAM: [========= ] 18.00%+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] }
Lock released on resource [tangnano20k]
Load SRAM: [=================== ] 38.00%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
Loading: [====== ] 11.11%[Pipeline] // stage
[Pipeline] }
Load SRAM: [============================= ] 58.00%
Loading: [============ ] 22.22%
Load SRAM: [======================================= ] 78.00%
Loading: [================= ] 33.33%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Loading: [======================= ] 44.45%Lock released on resource [nexys4]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [============================ ] 55.56%
Loading: [================================== ] 66.67%
Loading: [======================================= ] 77.78%
Loading: [============================================= ] 88.89%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ echo testando na ecp5
testando na ecp5
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
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