Skipping 968 KB..
Full LogTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTestTest
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
RESET_COUNTER | 00 | 01
IDLE | 01 | 10
INIT | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FETCH | 0000000000000001 | 0000
DECODE | 0000000000000010 | 0001
MEMADR | 0000000000000100 | 0010
MEMREAD | 0000000000001000 | 0011
MEMWB | 0000000000010000 | 0100
MEMWRITE | 0000000000100000 | 0101
EXECUTER | 0000000001000000 | 0110
EXECUTEI | 0000000010000000 | 1000
JAL | 0000000100000000 | 1001
BEQ | 0000001000000000 | 1010
AUIPC | 0000010000000000 | 1100
LUI | 0000100000000000 | 1101
JALR_PC | 0001000000000000 | 1110
JALR | 0010000000000000 | 1011
ALUWB | 0100000000000000 | 0111
EXECUTECSR | 1000000000000000 | 1111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'Control_Unit'
WARNING: [Synth 8-327] inferring latch for variable 'aluop_out_reg' [/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/alu_control.v:12]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_RECV | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_rx'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FSM_IDLE | 00 | 000
FSM_START | 11 | 001
FSM_SEND | 10 | 010
FSM_STOP | 01 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tool_tx'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8486 ; free virtual = 28500
---------------------------------------------------------------------------------
Info: at iteration #15, type ALL: wirelen solved = 30799, spread = 51346, legal = 52785; time = 0.45s
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 1
3 Input 32 Bit Adders := 1
2 Input 11 Bit Adders := 2
2 Input 6 Bit Adders := 4
2 Input 5 Bit Adders := 1
2 Input 4 Bit Adders := 2
+---XORs :
2 Input 32 Bit XORs := 1
+---Registers :
33 Bit Registers := 1
32 Bit Registers := 44
16 Bit Registers := 2
11 Bit Registers := 2
8 Bit Registers := 8
6 Bit Registers := 1
4 Bit Registers := 2
1 Bit Registers := 17
+---RAMs :
16K Bit (512 X 32 bit) RAMs := 1
64 Bit (8 X 8 bit) RAMs := 2
+---Muxes :
3 Input 33 Bit Muxes := 1
4 Input 32 Bit Muxes := 18
2 Input 32 Bit Muxes := 34
8 Input 32 Bit Muxes := 1
16 Input 32 Bit Muxes := 1
6 Input 32 Bit Muxes := 1
16 Input 16 Bit Muxes := 1
11 Input 16 Bit Muxes := 1
2 Input 16 Bit Muxes := 1
2 Input 8 Bit Muxes := 3
5 Input 8 Bit Muxes := 1
3 Input 6 Bit Muxes := 1
2 Input 6 Bit Muxes := 4
2 Input 5 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
8 Input 4 Bit Muxes := 1
23 Input 4 Bit Muxes := 1
10 Input 3 Bit Muxes := 1
2 Input 3 Bit Muxes := 1
3 Input 2 Bit Muxes := 1
2 Input 2 Bit Muxes := 14
16 Input 2 Bit Muxes := 3
4 Input 2 Bit Muxes := 4
3 Input 1 Bit Muxes := 6
2 Input 1 Bit Muxes := 49
16 Input 1 Bit Muxes := 6
4 Input 1 Bit Muxes := 2
13 Input 1 Bit Muxes := 2
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Info: at iteration #16, type ALL: wirelen solved = 31799, spread = 50993, legal = 52403; time = 0.53s
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "Immediate_Generator" instantiated to "Immediate_Generator" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":172)
WARN (NL0002) : The module "MUX" instantiated to "MemoryAddressMUX" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/core/core.v":84)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[0]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[1]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[2]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[3]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
WARN (NL0002) : The module "GPIO" instantiated to "Gpios[4]" is swept in optimizing("/var/lib/jenkins/workspace/Risco_5/Risco-5/src/peripheral/gpios.v":27)
[95%] Generate netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Info: at iteration #17, type ALL: wirelen solved = 31739, spread = 50716, legal = 52290; time = 0.36s
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6851] RAM (SOC/Memory/memory_reg) has partial Byte Wide Write Enable pattern, however no output register found in fanout of RAM. Recommended to use supported Byte Wide Write Enable template.
Info: at iteration #18, type ALL: wirelen solved = 32550, spread = 49245, legal = 51011; time = 0.40s
Info: at iteration #19, type ALL: wirelen solved = 33153, spread = 48674, legal = 50236; time = 0.38s
[100%] Generate report file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg"
Info: at iteration #20, type ALL: wirelen solved = 33159, spread = 48618, legal = 50122; time = 0.38s
Parsing netlist file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/pinout.cst"
Physical Constraint parsed completed
Running placement......
Info: at iteration #21, type ALL: wirelen solved = 33470, spread = 48253, legal = 49921; time = 0.52s
Info: at iteration #22, type ALL: wirelen solved = 34019, spread = 48505, legal = 50285; time = 0.37s
Info: at iteration #23, type ALL: wirelen solved = 34237, spread = 48471, legal = 50139; time = 0.37s
Info: at iteration #24, type ALL: wirelen solved = 33974, spread = 48741, legal = 50487; time = 0.37s
Info: at iteration #25, type ALL: wirelen solved = 34622, spread = 48140, legal = 49774; time = 0.44s
Info: at iteration #26, type ALL: wirelen solved = 34923, spread = 48041, legal = 49839; time = 0.48s
Info: at iteration #27, type ALL: wirelen solved = 34851, spread = 48621, legal = 50409; time = 0.38s
[10%] Placement Phase 0 completed
Info: at iteration #28, type ALL: wirelen solved = 35543, spread = 48106, legal = 49837; time = 0.38s
Info: at iteration #29, type ALL: wirelen solved = 35451, spread = 47554, legal = 49470; time = 0.37s
Info: at iteration #30, type ALL: wirelen solved = 35806, spread = 47705, legal = 49576; time = 0.53s
[20%] Placement Phase 1 completed
Info: at iteration #31, type ALL: wirelen solved = 36043, spread = 48110, legal = 50096; time = 0.37s
Info: at iteration #32, type ALL: wirelen solved = 36127, spread = 48277, legal = 50072; time = 0.37s
Info: at iteration #33, type ALL: wirelen solved = 36829, spread = 48261, legal = 49822; time = 0.37s
Info: at iteration #34, type ALL: wirelen solved = 36856, spread = 48170, legal = 49729; time = 0.37s
Info: HeAP Placer Time: 22.07s
Info: of which solving equations: 12.80s
Info: of which spreading cells: 1.67s
Info: of which strict legalisation: 0.51s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 18921, wirelen = 49470
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8181 ; free virtual = 28205
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8178 ; free virtual = 28201
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
Info: at iteration #5: temp = 0.000000, timing cost = 18828, wirelen = 43612
[30%] Placement Phase 2 completed
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8149 ; free virtual = 28173
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+-----------------------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+-----------------------------+-----------+----------------------+-----------------+
|top | SOC/Memory/memory_reg | Implied | 512 x 32 | RAM256X1S x 64 |
|top | SOC/Uart/RX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
|top | SOC/Uart/TX_FIFO/memory_reg | Implied | 8 x 8 | RAM32M x 2 |
+------------+-----------------------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8097 ; free virtual = 28121
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |BUFG | 1|
|2 |CARRY4 | 55|
|3 |LUT1 | 19|
|4 |LUT2 | 139|
|5 |LUT3 | 70|
|6 |LUT4 | 153|
|7 |LUT5 | 391|
|8 |LUT6 | 1334|
|9 |MUXF7 | 256|
|10 |RAM256X1S | 64|
|11 |RAM32M | 2|
|12 |RAM32X1D | 4|
|13 |FDRE | 1721|
|14 |FDSE | 5|
|15 |LD | 4|
|16 |IBUF | 2|
|17 |OBUF | 9|
|18 |OBUFT | 8|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 43 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2281.898 ; gain = 506.465 ; free physical = 8094 ; free virtual = 28118
Synthesis Optimization Complete : Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2281.898 ; gain = 657.250 ; free physical = 8094 ; free virtual = 28118
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2281.898 ; gain = 0.000 ; free physical = 8368 ; free virtual = 28392
INFO: [Netlist 29-17] Analyzing 385 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Info: at iteration #10: temp = 0.000000, timing cost = 20551, wirelen = 42012
Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2353.895 ; gain = 0.000 ; free physical = 8370 ; free virtual = 28394
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 74 instances were transformed.
LD => LDCE: 4 instances
RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 64 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete | Checksum: 2749c0b
INFO: [Common 17-83] Releasing license: Synthesis
75 Infos, 130 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:52 . Memory (MB): peak = 2353.930 ; gain = 1079.195 ; free physical = 8368 ; free virtual = 28391
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2059.762; main = 1783.795; forked = 422.428
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3227.508; main = 2353.898; forked = 969.656
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors, 8 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.75 . Memory (MB): peak = 2417.926 ; gain = 63.996 ; free physical = 8367 ; free virtual = 28391
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 15925b380
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2517.746 ; gain = 99.820 ; free physical = 8337 ; free virtual = 28361
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 15925b380
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 15925b380
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 1 Initialization | Checksum: 15925b380
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 15925b380
Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 15925b380
Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 2 Timer Update And Timing Data Collection | Checksum: 15925b380
Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 3 inverters resulting in an inversion of 9 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 2621db72c
Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Retarget | Checksum: 2621db72c
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 11 cells
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 2621db72c
Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Constant propagation | Checksum: 2621db72c
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 236eec1f4
Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2768.652 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Sweep | Checksum: 236eec1f4
INFO: [Opt 31-389] Phase Sweep created 8 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 236eec1f4
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
BUFG optimization | Checksum: 236eec1f4
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 236eec1f4
Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
Shift Register Optimization | Checksum: 236eec1f4
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 232eeb757
Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
Post Processing Netlist | Checksum: 232eeb757
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14806a170
Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.668 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Phase 9.2 Verifying Netlist Connectivity | Checksum: 14806a170
Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
Phase 9 Finalization | Checksum: 14806a170
Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 11 | 0 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 8 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 0 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 14806a170
Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2800.668 ; gain = 32.016 ; free physical = 8063 ; free virtual = 28087
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.668 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 14806a170
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.668 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 14806a170
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2800.668 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.668 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
Ending Netlist Obfuscation Task | Checksum: 14806a170
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2800.668 ; gain = 0.000 ; free physical = 8063 ; free virtual = 28087
INFO: [Common 17-83] Releasing license: Implementation
19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2800.668 ; gain = 446.738 ; free physical = 8063 ; free virtual = 28087
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.684 ; gain = 0.000 ; free physical = 8062 ; free virtual = 28086
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1105c4d3c
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2832.684 ; gain = 0.000 ; free physical = 8062 ; free virtual = 28086
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2832.684 ; gain = 0.000 ; free physical = 8062 ; free virtual = 28086
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: c2b9d6f2
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2832.684 ; gain = 0.000 ; free physical = 8062 ; free virtual = 28085
Phase 1.3 Build Placer Netlist Model
[50%] Placement Phase 3 completed
Running routing......
Phase 1.3 Build Placer Netlist Model | Checksum: 1035d4b79
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 8053 ; free virtual = 28077
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1035d4b79
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 8053 ; free virtual = 28077
Phase 1 Placer Initialization | Checksum: 1035d4b79
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 8051 ; free virtual = 28075
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1b8b689da
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 8042 ; free virtual = 28066
Phase 2.2 Update Timing before SLR Path Opt
Info: at iteration #15: temp = 0.000000, timing cost = 19199, wirelen = 41292
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1103ade3f
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 8041 ; free virtual = 28065
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1103ade3f
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 8041 ; free virtual = 28065
Phase 2.4 Global Placement Core
[60%] Routing Phase 0 completed
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: ceea6ed7
Time (s): cpu = 00:00:25 ; elapsed = 00:00:08 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7978 ; free virtual = 28002
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 48 LUTNM shape to break, 41 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 15, two critical 33, total 48, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 61 nets or LUTs. Breaked 48 LUTs, combined 13 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 7978 ; free virtual = 28002
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 48 | 13 | 61 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 48 | 13 | 61 | 0 | 9 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 18af9d291
Time (s): cpu = 00:00:27 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7978 ; free virtual = 28002
Phase 2.4 Global Placement Core | Checksum: 1b078c7e4
Time (s): cpu = 00:00:31 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7976 ; free virtual = 28000
Phase 2 Global Placement | Checksum: 1b078c7e4
Time (s): cpu = 00:00:31 ; elapsed = 00:00:09 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7976 ; free virtual = 28000
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1fb62ed45
Time (s): cpu = 00:00:32 ; elapsed = 00:00:10 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7976 ; free virtual = 28000
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c0f49b53
Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7976 ; free virtual = 28000
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1bbb47b6b
Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7974 ; free virtual = 27998
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1e1ede7bc
Time (s): cpu = 00:00:34 ; elapsed = 00:00:10 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7973 ; free virtual = 27997
Phase 3.5 Fast Optimization
Info: at iteration #20: temp = 0.000000, timing cost = 18518, wirelen = 41115
Phase 3.5 Fast Optimization | Checksum: 1db4cf242
Time (s): cpu = 00:00:39 ; elapsed = 00:00:14 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7971 ; free virtual = 27995
Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 144a82b42
Time (s): cpu = 00:00:41 ; elapsed = 00:00:15 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7974 ; free virtual = 27998
Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1467ad040
Time (s): cpu = 00:00:41 ; elapsed = 00:00:16 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7970 ; free virtual = 27994
Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 131d70474
Time (s): cpu = 00:00:41 ; elapsed = 00:00:16 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7970 ; free virtual = 27994
Phase 3.9 Fast Optimization
[70%] Routing Phase 1 completed
Phase 3.9 Fast Optimization | Checksum: 1760021b3
Time (s): cpu = 00:00:48 ; elapsed = 00:00:20 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7964 ; free virtual = 27988
Phase 3 Detail Placement | Checksum: 1760021b3
Time (s): cpu = 00:00:48 ; elapsed = 00:00:20 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7964 ; free virtual = 27988
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 37f1a22c
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.071 | TNS=-52.440 |
Phase 1 Physical Synthesis Initialization | Checksum: 5d771248
Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.3 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 7966 ; free virtual = 27990
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 5d771248
Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 7967 ; free virtual = 27991
Phase 4.1.1.1 BUFG Insertion | Checksum: 37f1a22c
Time (s): cpu = 00:00:51 ; elapsed = 00:00:21 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7967 ; free virtual = 27991
Phase 4.1.1.2 Post Placement Timing Optimization
Info: at iteration #25: temp = 0.000000, timing cost = 19070, wirelen = 41042
[80%] Routing Phase 2 completed
Info: at iteration #30: temp = 0.000000, timing cost = 18272, wirelen = 41008
Info: at iteration #30: temp = 0.000000, timing cost = 18257, wirelen = 41008
Info: SA placement time 58.59s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 29.23 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.24 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.28 ns
Info: Slack histogram:
Info: legend: * represents 144 endpoint(s)
Info: + represents [1,144) endpoint(s)
Info: [ 5786, 7459) |+
Info: [ 7459, 9132) |*+
Info: [ 9132, 10805) |********+
Info: [ 10805, 12478) |****+
Info: [ 12478, 14151) |+
Info: [ 14151, 15824) |******+
Info: [ 15824, 17497) |*************+
Info: [ 17497, 19170) |*************+
Info: [ 19170, 20843) |************************************************************
Info: [ 20843, 22516) |***********************************************************+
Info: [ 22516, 24189) |******+
Info: [ 24189, 25862) |**+
Info: [ 25862, 27535) |**+
Info: [ 27535, 29208) |+
Info: [ 29208, 30881) |+
Info: [ 30881, 32554) |+
Info: [ 32554, 34227) |**+
Info: [ 34227, 35900) |**+
Info: [ 35900, 37573) |+
Info: [ 37573, 39246) |*+
Info: Checksum: 0x67560895
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 66293 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 107 892 | 107 892 | 65690| 1.26 1.26|
Info: 2000 | 238 1761 | 131 869 | 65018| 0.30 1.56|
Info: 3000 | 417 2582 | 179 821 | 64399| 0.36 1.92|
Info: 4000 | 568 3431 | 151 849 | 63866| 0.37 2.29|
Info: 5000 | 725 4274 | 157 843 | 63356| 0.32 2.60|
Info: 6000 | 826 5173 | 101 899 | 63127| 0.38 2.99|
Info: 7000 | 979 6020 | 153 847 | 62787| 0.37 3.36|
Info: 8000 | 1098 6901 | 119 881 | 62146| 0.34 3.70|
Info: 9000 | 1226 7773 | 128 872 | 62004| 0.38 4.09|
WARN (PR1014) : Generic routing resource will be used to clock signal 'clk_d' by the specified constraint. And then it may lead to the excessive delay or skew
[90%] Routing Phase 3 completed
Info: 10000 | 1332 8667 | 106 894 | 61359| 0.38 4.47|
Running timing analysis......
Info: 11000 | 1458 9541 | 126 874 | 60763| 0.37 4.83|
Info: 12000 | 1619 10380 | 161 839 | 60430| 0.45 5.28|
Info: 13000 | 1769 11230 | 150 850 | 60250| 0.42 5.71|
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.017. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: bfbf9288
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Phase 4.1 Post Commit Optimization | Checksum: bfbf9288
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: bfbf9288
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 1x1| 4x4|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: bfbf9288
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Phase 4.3 Placer Reporting | Checksum: bfbf9288
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 7957 ; free virtual = 27981
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Phase 4 Post Placement Optimization and Clean-Up | Checksum: f21d45c8
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
Ending Placer Task | Checksum: ef006d9e
Time (s): cpu = 00:01:13 ; elapsed = 00:00:39 . Memory (MB): peak = 2839.711 ; gain = 7.027 ; free physical = 7957 ; free virtual = 27981
37 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:15 ; elapsed = 00:00:40 . Memory (MB): peak = 2839.711 ; gain = 39.043 ; free physical = 7957 ; free virtual = 27981
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
Info: 14000 | 1899 12100 | 130 870 | 59702| 0.34 6.05|
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 7954 ; free virtual = 27978
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
Info: 15000 | 2058 12941 | 159 841 | 59256| 0.40 6.44|
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 7958 ; free virtual = 27982
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Info: 16000 | 2197 13802 | 139 861 | 58687| 0.43 6.87|
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 17000 | 2347 14652 | 150 850 | 57985| 0.41 7.28|
Info: 18000 | 2498 15501 | 151 849 | 57523| 0.36 7.64|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 970cab0f ConstDB: 0 ShapeSum: 57f3c28f RouteDB: 0
Info: 19000 | 2643 16356 | 145 855 | 57031| 0.50 8.14|
Info: 20000 | 2822 17177 | 179 821 | 56920| 0.40 8.54|
Info: 21000 | 2954 18045 | 132 868 | 56544| 0.42 8.97|
Info: 22000 | 3085 18914 | 131 869 | 56091| 0.40 9.36|
Info: 23000 | 3215 19784 | 130 870 | 55589| 0.39 9.75|
Info: 24000 | 3345 20654 | 130 870 | 55534| 0.33 10.09|
Info: 25000 | 3483 21516 | 138 862 | 55266| 0.40 10.49|
Info: 26000 | 3596 22403 | 113 887 | 54675| 0.39 10.88|
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.power.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.pin.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.html" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.rpt.txt" completed
Generate file "/var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/tangnano20k/impl/pnr/project.tr.html" completed
Mon Apr 15 02:07:06 2024
[Pipeline] }
[Pipeline] // stage
Info: 27000 | 3748 23251 | 152 848 | 54235| 0.45 11.33|
[Pipeline] }
Info: 28000 | 3904 24095 | 156 844 | 54284| 0.35 11.68|
Info: 29000 | 4028 24971 | 124 876 | 53841| 0.38 12.06|
Info: 30000 | 4102 25897 | 74 926 | 53610| 0.35 12.41|
Info: 31000 | 4189 26810 | 87 913 | 53503| 0.39 12.80|
Info: 32000 | 4296 27703 | 107 893 | 52783| 0.39 13.19|
Info: 33000 | 4426 28573 | 130 870 | 52389| 0.57 13.75|
Info: 34000 | 4554 29445 | 128 872 | 52809| 0.65 14.40|
Info: 35000 | 4686 30313 | 132 868 | 52195| 0.39 14.79|
Info: 36000 | 4806 31193 | 120 880 | 51628| 0.44 15.23|
Info: 37000 | 4930 32069 | 124 876 | 51181| 0.42 15.64|
Info: 38000 | 4995 33004 | 65 935 | 51448| 0.36 16.01|
Info: 39000 | 5097 33902 | 102 898 | 51345| 0.36 16.37|
Info: 40000 | 5192 34807 | 95 905 | 50897| 0.35 16.72|
Info: 41000 | 5318 35681 | 126 874 | 50757| 0.39 17.12|
Info: 42000 | 5402 36597 | 84 916 | 50880| 0.32 17.44|
Info: 43000 | 5493 37506 | 91 909 | 50235| 0.32 17.76|
Info: 44000 | 5572 38427 | 79 921 | 49770| 0.38 18.14|
Info: 45000 | 5733 39266 | 161 839 | 49274| 0.39 18.52|
Info: 46000 | 5872 40127 | 139 861 | 48685| 0.43 18.95|
Info: 47000 | 6075 40924 | 203 797 | 48644| 0.45 19.40|
Info: 48000 | 6267 41732 | 192 808 | 48928| 0.47 19.87|
Info: 49000 | 6367 42632 | 100 900 | 48732| 0.49 20.36|
Info: 50000 | 6486 43513 | 119 881 | 48044| 0.44 20.79|
Info: 51000 | 6654 44345 | 168 832 | 47447| 0.44 21.23|
Info: 52000 | 6789 45210 | 135 865 | 47067| 0.39 21.62|
Info: 53000 | 6891 46108 | 102 898 | 46959| 0.40 22.01|
Info: 54000 | 6919 47080 | 28 972 | 46678| 0.34 22.36|
Info: 55000 | 7100 47899 | 181 819 | 46136| 0.44 22.80|
Info: 56000 | 7190 48809 | 90 910 | 46244| 0.38 23.18|
Info: 57000 | 7248 49751 | 58 942 | 45486| 0.49 23.67|
Info: 58000 | 7407 50592 | 159 841 | 44899| 0.47 24.15|
Info: 59000 | 7539 51460 | 132 868 | 44252| 0.40 24.55|
Info: 60000 | 7709 52290 | 170 830 | 44484| 0.41 24.97|
Info: 61000 | 7786 53213 | 77 923 | 43725| 0.53 25.49|
Info: 62000 | 7942 54057 | 156 844 | 44145| 0.39 25.88|
Info: 63000 | 7950 55049 | 8 992 | 43177| 0.30 26.18|
Info: 64000 | 8127 55872 | 177 823 | 42564| 0.41 26.59|
Info: 65000 | 8341 56658 | 214 786 | 42917| 0.46 27.05|
Info: 66000 | 8518 57481 | 177 823 | 42716| 0.49 27.54|
Info: 67000 | 8702 58297 | 184 816 | 42358| 0.48 28.02|
Info: 68000 | 8839 59160 | 137 863 | 42613| 0.46 28.48|
Info: 69000 | 8865 60134 | 26 974 | 42632| 0.51 28.99|
Info: 70000 | 8908 61091 | 43 957 | 41721| 0.50 29.48|
Info: 71000 | 9110 61889 | 202 798 | 41204| 0.44 29.92|
Info: 72000 | 9187 62812 | 77 923 | 41129| 0.38 30.30|
Info: 73000 | 9274 63725 | 87 913 | 41234| 0.52 30.82|
Info: 74000 | 9433 64566 | 159 841 | 40898| 0.52 31.34|
Info: 75000 | 9616 65383 | 183 817 | 40541| 0.44 31.78|
Info: 76000 | 9775 66224 | 159 841 | 39926| 0.41 32.19|
Info: 77000 | 9952 67047 | 177 823 | 39705| 0.51 32.70|
Info: 78000 | 10069 67930 | 117 883 | 39210| 0.40 33.10|
Info: 79000 | 10218 68781 | 149 851 | 38671| 0.45 33.55|
Info: 80000 | 10440 69559 | 222 778 | 38568| 0.41 33.96|
Info: 81000 | 10583 70416 | 143 857 | 38464| 0.61 34.57|
Info: 82000 | 10779 71220 | 196 804 | 37998| 0.57 35.14|
Info: 83000 | 10927 72072 | 148 852 | 37558| 0.53 35.68|
Info: 84000 | 11096 72903 | 169 831 | 36889| 0.49 36.16|
Info: 85000 | 11264 73735 | 168 832 | 36614| 0.59 36.76|
Info: 86000 | 11392 74607 | 128 872 | 36927| 0.71 37.47|
Info: 87000 | 11490 75509 | 98 902 | 36332| 0.64 38.11|
Info: 88000 | 11665 76334 | 175 825 | 36197| 0.57 38.68|
Info: 89000 | 11742 77257 | 77 923 | 37068| 0.50 39.18|
Info: 90000 | 11846 78153 | 104 896 | 36564| 0.47 39.65|
Post Restoration Checksum: NetGraph: 9d600986 | NumContArr: 5d0968c3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 27fbb6783
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8249 ; free virtual = 28280
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 27fbb6783
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8252 ; free virtual = 28283
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 27fbb6783
Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8252 ; free virtual = 28283
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 200092481
Time (s): cpu = 00:00:37 ; elapsed = 00:00:28 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8236 ; free virtual = 28267
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.253 | TNS=0.000 | WHS=-0.153 | THS=-12.672|
Router Utilization Summary
Global Vertical Routing Utilization = 0.00073987 %
Global Horizontal Routing Utilization = 0.0004973 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 3354
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 3351
Number of Partially Routed Nets = 3
Number of Node Overlaps = 1
Phase 2 Router Initialization | Checksum: 271a90c68
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8236 ; free virtual = 28267
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 271a90c68
Time (s): cpu = 00:00:39 ; elapsed = 00:00:29 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8236 ; free virtual = 28267
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 155d4214f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8226 ; free virtual = 28257
Phase 3 Initial Routing | Checksum: 155d4214f
Time (s): cpu = 00:00:43 ; elapsed = 00:00:30 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8229 ; free virtual = 28261
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 1680
Info: 91000 | 11953 79046 | 107 893 | 35899| 0.57 40.23|
Number of Nodes with overlaps = 615
Info: 92000 | 12162 79837 | 209 791 | 35574| 0.63 40.86|
Info: 93000 | 12345 80654 | 183 817 | 35176| 0.64 41.50|
Info: 94000 | 12525 81474 | 180 820 | 35066| 0.65 42.15|
Number of Nodes with overlaps = 362
Info: 95000 | 12615 82384 | 90 910 | 35015| 0.60 42.75|
Info: 96000 | 12755 83244 | 140 860 | 34622| 0.61 43.35|
Number of Nodes with overlaps = 240
Info: 97000 | 12906 84093 | 151 849 | 34463| 0.66 44.01|
Info: 98000 | 13147 84852 | 241 759 | 33848| 0.57 44.59|
Info: 99000 | 13283 85716 | 136 864 | 34360| 0.55 45.14|
Number of Nodes with overlaps = 145
Info: 100000 | 13435 86564 | 152 848 | 34035| 0.57 45.71|
Info: 101000 | 13600 87399 | 165 835 | 33375| 0.59 46.31|
Number of Nodes with overlaps = 76
Info: 102000 | 13801 88198 | 201 799 | 32728| 0.52 46.83|
Info: 103000 | 14094 88905 | 293 707 | 32271| 0.61 47.44|
Number of Nodes with overlaps = 50
Info: 104000 | 14319 89680 | 225 775 | 31739| 0.67 48.11|
Info: 105000 | 14585 90414 | 266 734 | 31238| 0.56 48.67|
Number of Nodes with overlaps = 29
Info: 106000 | 14869 91130 | 284 716 | 30837| 0.54 49.21|
Number of Nodes with overlaps = 19
Info: 107000 | 15284 91715 | 415 585 | 30461| 0.50 49.71|
Number of Nodes with overlaps = 12
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 2
Info: 108000 | 15530 92469 | 246 754 | 30191| 0.48 50.19|
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.028 | TNS=-83.943| WHS=N/A | THS=N/A |
Info: 109000 | 15888 93111 | 358 642 | 29811| 0.57 50.76|
Phase 4.1 Global Iteration 0 | Checksum: 232d7c8b4
Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8223 ; free virtual = 28254
Phase 4.2 Global Iteration 1
Info: 110000 | 16217 93782 | 329 671 | 29483| 0.53 51.29|
Number of Nodes with overlaps = 766
Info: 111000 | 16563 94436 | 346 654 | 29000| 0.57 51.86|
Info: 112000 | 16954 95045 | 391 609 | 28516| 0.68 52.54|
Info: 113000 | 17302 95697 | 348 652 | 28329| 0.69 53.23|
Number of Nodes with overlaps = 412
Info: 114000 | 17702 96297 | 400 600 | 28004| 0.66 53.89|
Info: 115000 | 17861 97138 | 159 841 | 28182| 0.63 54.53|
Number of Nodes with overlaps = 240
Info: 116000 | 18177 97822 | 316 684 | 27817| 0.64 55.17|
Info: 117000 | 18637 98362 | 460 540 | 27506| 0.65 55.81|
Number of Nodes with overlaps = 166
Info: 118000 | 18930 99069 | 293 707 | 29154| 0.75 56.56|
Number of Nodes with overlaps = 97
Info: 119000 | 18965 100034 | 35 965 | 28215| 0.67 57.23|
Info: 120000 | 19024 100975 | 59 941 | 29041| 0.69 57.92|
Number of Nodes with overlaps = 76
Info: 121000 | 19112 101887 | 88 912 | 28464| 0.73 58.65|
Info: 122000 | 19168 102831 | 56 944 | 27762| 0.51 59.16|
Number of Nodes with overlaps = 29
Number of Nodes with overlaps = 17
Info: 123000 | 19377 103622 | 209 791 | 27144| 0.61 59.76|
Number of Nodes with overlaps = 12
Info: 124000 | 19802 104197 | 425 575 | 26768| 0.53 60.30|
Number of Nodes with overlaps = 5
Number of Nodes with overlaps = 4
Info: 125000 | 20200 104799 | 398 602 | 26505| 0.59 60.89|
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 1
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.071 | TNS=-73.151| WHS=N/A | THS=N/A |
Phase 4.2 Global Iteration 1 | Checksum: 26bbe5f40
Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8214 ; free virtual = 28246
Phase 4 Rip-up And Reroute | Checksum: 26bbe5f40
Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8214 ; free virtual = 28246
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1.1 Update Timing
Info: 126000 | 20596 105403 | 396 604 | 26165| 0.61 61.50|
Phase 5.1.1 Update Timing | Checksum: 26a5b9294
Time (s): cpu = 00:01:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8214 ; free virtual = 28246
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.948 | TNS=-73.824| WHS=N/A | THS=N/A |
Number of Nodes with overlaps = 0
Phase 5.1 Delay CleanUp | Checksum: 2bd066f60
Time (s): cpu = 00:01:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2bd066f60
Time (s): cpu = 00:01:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 5 Delay and Skew Optimization | Checksum: 2bd066f60
Time (s): cpu = 00:01:45 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2d7fffb2b
Time (s): cpu = 00:01:46 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.886 | TNS=-74.673| WHS=0.081 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 2d7fffb2b
Time (s): cpu = 00:01:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 6 Post Hold Fix | Checksum: 2d7fffb2b
Time (s): cpu = 00:01:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 1.07046 %
Global Horizontal Routing Utilization = 1.36367 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
--GLOBAL Congestion:
Utilization threshold used for congestion level computation: 0.85
Congestion Report
North Dir 1x1 Area, Max Cong = 64.8649%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 66.6667%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 72.0588%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 75%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 2d7fffb2b
Time (s): cpu = 00:01:47 ; elapsed = 00:00:54 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2d7fffb2b
Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Phase 9 Depositing Routes
Info: 127000 | 21043 105956 | 447 553 | 25887| 0.64 62.14|
Info: 128000 | 21496 106503 | 453 547 | 25568| 0.48 62.62|
Phase 9 Depositing Routes | Checksum: 2b42b6adb
Time (s): cpu = 00:01:47 ; elapsed = 00:00:55 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28244
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=-0.886 | TNS=-74.673| WHS=0.081 | THS=0.000 |
WARNING: [Route 35-328] Router estimated timing not met.
Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design.
Phase 10 Post Router Timing | Checksum: 2b42b6adb
Time (s): cpu = 00:01:48 ; elapsed = 00:00:55 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: d1cd68ab
Time (s): cpu = 00:01:48 ; elapsed = 00:00:55 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Ending Routing Task | Checksum: d1cd68ab
Time (s): cpu = 00:01:48 ; elapsed = 00:00:55 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:51 ; elapsed = 00:00:56 . Memory (MB): peak = 2839.711 ; gain = 0.000 ; free physical = 8213 ; free virtual = 28245
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 129000 | 22002 106997 | 506 494 | 25220| 0.49 63.11|
Info: 130000 | 22492 107507 | 490 510 | 24980| 0.64 63.75|
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Inter-SLR Compensation : Conservative
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (12)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (4)
5. checking no_input_delay (1)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (12)
-------------------------
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[6]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[7]/Q (HIGH)
There are 4 register/latch pins with no clock driven by root clock pin: SOC/Core/Control_Unit/FSM_onehot_state_reg[9]/Q (HIGH)
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (4)
------------------------------------------------
There are 4 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (1)
------------------------------
There is 1 input port with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (9)
-------------------------------
There are 9 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
-0.887 -74.687 198 6655 0.081 0.000 0 6655 3.750 0.000 0 2015
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
sys_clk_pin {0.000 5.000} 10.000 100.000
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
sys_clk_pin -0.887 -74.687 198 6655 0.081 0.000 0 6655 3.750 0.000 0 2015
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
Info: 131000 | 23026 107973 | 534 466 | 24731| 0.60 64.35|
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
Info: 132000 | 23584 108415 | 558 442 | 24433| 0.49 64.84|
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/Risco_5/Risco-5/fpga/nexys4_ddr/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
Info: 133000 | 23779 109220 | 195 805 | 24704| 1.02 65.86|
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...
Info: 134000 | 24096 109903 | 317 683 | 24391| 0.83 66.69|
Finished Running Vector-less Activity Propagation
Info: 135000 | 24576 110423 | 480 520 | 24105| 0.53 67.22|
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "./build/out.bit"
Command: write_bitstream -force ./build/out.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
Info: 136000 | 25084 110915 | 508 492 | 23850| 0.48 67.71|
Info: 137000 | 25541 111458 | 457 543 | 23734| 0.47 68.18|
Info: 138000 | 25979 112020 | 438 562 | 23623| 0.54 68.72|
Info: 139000 | 26340 112659 | 361 639 | 23309| 0.51 69.23|
Info: 140000 | 26852 113147 | 512 488 | 23016| 0.49 69.72|
Info: 141000 | 27206 113793 | 354 646 | 22850| 0.54 70.26|
Info: 142000 | 27531 114468 | 325 675 | 22731| 0.53 70.79|
Info: 143000 | 28053 114946 | 522 478 | 22406| 0.48 71.27|
Info: 144000 | 28488 115499 | 435 553 | 21961| 0.44 71.71|
Info: 145000 | 28814 116168 | 326 669 | 21983| 0.50 72.20|
Info: 146000 | 29043 116934 | 229 766 | 21629| 0.50 72.71|
Info: 147000 | 29452 117510 | 409 576 | 21270| 0.45 73.16|
Info: 148000 | 29812 118113 | 360 603 | 20705| 0.33 73.49|
Info: 149000 | 30174 118703 | 362 590 | 20207| 0.38 73.87|
Info: 150000 | 30519 119336 | 345 633 | 19847| 0.43 74.30|
Info: 151000 | 30858 119965 | 339 629 | 19457| 0.41 74.70|
Info: 152000 | 31224 120558 | 366 593 | 18993| 0.39 75.09|
Info: 153000 | 31671 121069 | 447 511 | 18563| 0.39 75.48|
Info: 154000 | 32179 121519 | 508 450 | 18167| 0.41 75.89|
Info: 155000 | 32731 121928 | 552 409 | 17805| 0.43 76.32|
Info: 156000 | 33254 122358 | 523 430 | 17466| 0.46 76.78|
Info: 157000 | 33814 122762 | 560 404 | 17154| 0.46 77.24|
Info: 158000 | 34350 123177 | 536 415 | 16785| 0.49 77.73|
Info: 159000 | 34826 123629 | 476 452 | 16341| 0.51 78.24|
Info: 160000 | 35217 124137 | 391 508 | 15807| 0.41 78.65|
Info: 161000 | 35396 124934 | 179 797 | 15698| 0.47 79.12|
Info: 162000 | 35618 125529 | 222 595 | 14993| 0.32 79.44|
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC PDRC-153] Gated clock check: Net SOC/Core/Control_Unit/FSM_onehot_state_reg[9]_0[0] is a gated clock net sourced by a combinational pin SOC/Core/Control_Unit/aluop_out_reg[3]_i_2/O, cell SOC/Core/Control_Unit/aluop_out_reg[3]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Info: 163000 | 35753 126205 | 135 676 | 14136| 0.24 79.68|
Info: 164000 | 35777 127119 | 24 914 | 13161| 0.17 79.85|
Info: 165000 | 35795 128070 | 18 951 | 12179| 0.16 80.01|
Info: 166000 | 35818 129029 | 23 959 | 11204| 0.16 80.17|
Info: 167000 | 35827 130007 | 9 978 | 10214| 0.15 80.32|
Info: 168000 | 35852 130974 | 25 967 | 9242| 0.15 80.47|
Info: 169000 | 35855 131965 | 3 991 | 8245| 0.14 80.61|
Info: 170000 | 35863 132949 | 8 984 | 7253| 0.14 80.75|
Info: 171000 | 35875 133931 | 12 982 | 6266| 0.15 80.90|
Info: 172000 | 35884 134919 | 9 988 | 5278| 0.15 81.05|
Info: 173000 | 35907 135888 | 23 969 | 4303| 0.16 81.21|
Info: 174000 | 35928 136861 | 21 973 | 3325| 0.16 81.36|
Info: 175000 | 36036 137733 | 108 872 | 2454| 0.27 81.64|
Loading site data...
Info: 176000 | 36272 138471 | 236 738 | 1822| 0.43 82.06|
Info: 177000 | 36410 139225 | 138 754 | 1188| 0.51 82.57|
Info: 178000 | 36447 139956 | 37 731 | 234| 0.39 82.96|
Info: 178233 | 36447 140073 | 0 117 | 0| 0.20 83.16|
Info: Routing complete.
Info: Router1 time 83.16s
Loading route data...
Processing options...
Creating bitmap...
Info: Checksum: 0xa376a95d
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info: 0.5 0.5 Source SOC.Core.Control_Unit.state_TRELLIS_FF_Q_3.Q
Info: 1.8 2.3 Net SOC.Core.Alu.ALU_out_S_LUT4_Z_2_B_LUT4_A_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_LUT4_Z_D[1] (34,31) -> (40,21)
Info: Sink SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: Risco-5/src/core/control_unit.v:51.11-51.16
Info: 0.2 2.6 Source SOC.Memory.address_LUT4_Z_C_LUT4_Z_D_LUT4_Z.F
Info: 1.7 4.2 Net SOC.Memory.address_LUT4_Z_C_LUT4_Z_D[2] (40,21) -> (35,8)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 4.5 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_LUT4_Z.F
Info: 1.9 6.4 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1 (35,8) -> (37,18)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.B
Info: 0.4 6.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB0.FCO
Info: 0.0 6.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCI
Info: 0.0 6.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0$CCU2_COMB1.FCO
Info: 0.0 6.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT (37,18) -> (37,18)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 6.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB0.FCO
Info: 0.0 6.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCI
Info: 0.0 6.9 Source SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN$CCU2_COMB1.FCO
Info: 0.0 6.9 Net SOC.Memory.address_LUT4_Z_C_CCU2C_B1_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_B1_CCU2C_B0_COUT_CCU2C_CIN_COUT (37,18) -> (37,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.0 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.0 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.0 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.0 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (37,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.1 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.1 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.2 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.2 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.2 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.2 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.2 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.2 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.2 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.2 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.3 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.3 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (38,18) -> (38,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.3 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.3 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1_CIN (38,18) -> (39,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.4 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.4 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (39,18) -> (39,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.4 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_CIN_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.4 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1_CIN (39,18) -> (39,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCI
Info: Defined in:
Info: Risco-5/src/peripheral/bus.v:54.5-54.37
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info: 0.1 7.4 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB0.FCO
Info: 0.0 7.4 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_FCI_INT (39,18) -> (39,18)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCI
Info: 0.0 7.4 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1$CCU2_COMB1.FCO
Info: 0.0 7.4 Net $nextpnr_CCU2C_1$CIN (39,18) -> (39,18)
Info: Sink $nextpnr_CCU2C_1$CCU2_COMB0.FCI
Info: 0.4 7.9 Source $nextpnr_CCU2C_1$CCU2_COMB0.F
Info: 1.0 8.9 Net SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B0_CCU2C_B1_COUT (39,18) -> (38,21)
Info: Sink SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B1_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 9.1 Source SOC.Uart.RX_FIFO.memory.0.0_DO_3_LUT4_Z_3_D_CCU2C_COUT_B1_LUT4_C.F
Info: 2.7 11.8 Net SOC.Bus.slave_1_write_LUT4_Z_C[1] (38,21) -> (17,39)
Info: Sink SOC.Memory.address_LUT4_Z.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 12.0 Source SOC.Memory.address_LUT4_Z.F
Info: 3.6 15.6 Net SOC.slave_address[5] (17,39) -> (14,4)
Info: Sink SOC.Memory.memory.0.771$DPRAM_COMB3.A
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:22.5-22.18
Info: 0.2 15.8 Source SOC.Memory.memory.0.771$DPRAM_COMB3.F
Info: 0.9 16.7 Net SOC.Memory.memory.0.771_DO[3] (14,4) -> (13,4)
Info: Sink SOC.Memory.memory.0.771_DO_LUT4_C.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 17.0 Source SOC.Memory.memory.0.771_DO_LUT4_C.F
Info: 0.9 17.8 Net SOC.Memory.memory.0.771_DO_LUT4_C_Z[3] (13,4) -> (13,6)
Info: Sink SOC.Memory.memory.0.771_DO_LUT4_C_Z_LUT4_A.D
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 18.1 Source SOC.Memory.memory.0.771_DO_LUT4_C_Z_LUT4_A.F
Info: 1.6 19.6 Net SOC.Memory.memory.0.459_DO_LUT4_C_Z_LUT4_A_Z[2] (13,6) -> (21,14)
Info: Sink SOC.Memory.memory.0.987_DO_LUT4_C_Z_LUT4_A_Z_LUT4_Z_1.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.2 19.9 Source SOC.Memory.memory.0.987_DO_LUT4_C_Z_LUT4_A_Z_LUT4_Z_1.F
Info: 0.9 20.7 Net SOC.Memory.memory.0.987_DO_LUT4_C_Z_LUT4_A_Z[4] (21,14) -> (22,16)
Info: Sink SOC.Memory.memory.0.403_DO_LUT4_C_Z_LUT4_B_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.0 Source SOC.Memory.memory.0.403_DO_LUT4_C_Z_LUT4_B_Z_LUT4_C_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 0.4 21.4 Net SOC.Memory.memory.0.403_DO_LUT4_C_Z_LUT4_B_Z_LUT4_C_Z[4] (22,16) -> (22,16)
Info: Sink SOC.Memory.memory.0.727_DO_LUT4_C_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.M
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.3 21.6 Source SOC.Memory.memory.0.727_DO_LUT4_C_Z_LUT4_A_Z_LUT4_C_Z_LUT4_C_Z_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: 3.1 24.7 Net SOC.Core.read_data_LUT4_Z_13_D[0] (22,16) -> (40,43)
Info: Sink SOC.Core.read_data_PFUMX_Z_10_BLUT_LUT4_Z.C
Info: Defined in:
Info: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info: 0.4 25.1 Source SOC.Core.read_data_PFUMX_Z_10_BLUT_LUT4_Z.OFX
Info: 0.9 26.1 Net SOC.read_data[23] (40,43) -> (40,39)
Info: Sink SOC.Core.memory_register_TRELLIS_FF_Q_8.M
Info: Defined in:
Info: Risco-5/src/peripheral/soc.v:21.34-21.43
Info: 0.0 26.1 Setup SOC.Core.memory_register_TRELLIS_FF_Q_8.M
Info: 4.8 ns logic, 21.3 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: curr total
Info: 0.0 0.0 Source rx$tr_io.O
Info: 2.5 2.5 Net rx$TRELLIS_IO_IN (90,20) -> (68,5)
Info: Sink SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:4.16-4.18
Info: 0.0 2.5 Setup SOC.Uart.i_uart_rx.rxd_reg_0_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 2.5 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info: 0.5 0.5 Source SOC.Leds.data_TRELLIS_FF_Q_29.Q
Info: 1.9 2.5 Net SOC.Core.read_data_LUT4_Z_2_C[0] (41,31) -> (60,36)
Info: Sink led_LUT4_Z_6.D
Info: Defined in:
Info: Risco-5/src/peripheral/leds.v:15.12-15.16
Info: 0.2 2.7 Source led_LUT4_Z_6.F
Info: 2.7 5.4 Net led[2]$TRELLIS_IO_OUT (60,36) -> (90,44)
Info: Sink led[2]$tr_io.I
Info: Defined in:
Info: Risco-5/fpga/ecp5/main.v:6.22-6.25
Info: 0.8 ns logic, 4.6 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 38.33 MHz (PASS at 25.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 2.51 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 5.39 ns
Info: Slack histogram:
Info: legend: * represents 211 endpoint(s)
Info: + represents [1,211) endpoint(s)
Info: [ 13911, 15169) |+
Info: [ 15169, 16427) |***+
Info: [ 16427, 17685) |*****+
Info: [ 17685, 18943) |+
Info: [ 18943, 20201) |+
Info: [ 20201, 21459) |***+
Info: [ 21459, 22717) |*********+
Info: [ 22717, 23975) |******+
Info: [ 23975, 25233) |********************+
Info: [ 25233, 26491) |************************************************************
Info: [ 26491, 27749) |*********+
Info: [ 27749, 29007) |*+
Info: [ 29007, 30265) |*+
Info: [ 30265, 31523) |*+
Info: [ 31523, 32781) |+
Info: [ 32781, 34039) |+
Info: [ 34039, 35297) |+
Info: [ 35297, 36555) |*+
Info: [ 36555, 37813) |*+
Info: [ 37813, 39071) |+
Creating bitstream...
Writing bitstream ./build/out.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3152.906 ; gain = 229.332 ; free physical = 8285 ; free virtual = 28364
Info: Program finished normally.
[Pipeline] }
INFO: [Common 17-206] Exiting Vivado at Mon Apr 15 02:08:21 2024...
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] stage
[Pipeline] { (ECPPACK)
[Pipeline] sh
+ /eda/oss-cad-suite/bin/ecppack --compress --input ./build/out.config --bit ./build/out.bit
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Flash)
[Pipeline] parallel
[Pipeline] { (Branch: openFPGAloader ECP5)
[Pipeline] { (Branch: openFPGAloader Tangnano 20k)
[Pipeline] { (Branch: openFPGAloader Nexys 4 DDR)
[Pipeline] stage
[Pipeline] { (openFPGAloader ECP5)
[Pipeline] stage
[Pipeline] { (openFPGAloader Tangnano 20k)
[Pipeline] stage
[Pipeline] { (openFPGAloader Nexys 4 DDR)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
+ /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 ./build/out.bit
empty
Found 1 compatible device:
0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE
[Pipeline] sh
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo gravando na tang nano
gravando na tang nano
[Pipeline] sh
[Pipeline] }
+ cd Risco-5/fpga/nexys4_ddr
+ /eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 ./build/out.bit
empty
Jtag frequency : requested 6.00MHz -> real 6.00MHz
Open file DONE
Parse file DONE
load program
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
Loading: [==== ] 7.94%[Pipeline] }
Load SRAM: [========= ] 18.00%[Pipeline] // stage
[Pipeline] }
Loading: [======== ] 15.87%
Load SRAM: [=================== ] 38.00%
Loading: [============ ] 23.81%
Load SRAM: [============================= ] 58.00%
Loading: [================ ] 31.74%
Load SRAM: [======================================= ] 78.00%
Loading: [==================== ] 39.68%
Load SRAM: [================================================= ] 98.00%
Load SRAM: [===================================================] 100.00%
Done
[Pipeline] }
Lock released on resource [nexys4]
Loading: [======================== ] 47.61%[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Loading: [============================ ] 55.55%
Loading: [================================ ] 63.48%
Loading: [==================================== ] 71.42%
Loading: [======================================== ] 79.35%
Loading: [============================================ ] 87.29%
Loading: [================================================ ] 95.22%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE
[Pipeline] }
Lock released on resource [ecp5]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // script
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Testes)
[Pipeline] parallel
[Pipeline] { (Branch: ECP5 - Testes)
[Pipeline] { (Branch: TangNano - Testes)
[Pipeline] { (Branch: Nexys 4 - Testes)
[Pipeline] stage
[Pipeline] { (ECP5 - Testes)
[Pipeline] stage
[Pipeline] { (TangNano - Testes)
[Pipeline] stage
[Pipeline] { (Nexys 4 - Testes)
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] script
[Pipeline] {
[Pipeline] echo
Rodando teste na ECP5
[Pipeline] lock
Trying to acquire lock on [ecp5]
Resource [ecp5] did not exist. Created.
Lock acquired on [ecp5]
[Pipeline] {
[Pipeline] echo
Rodando teste na tang nano
[Pipeline] lock
Trying to acquire lock on [tangnano20k]
Resource [tangnano20k] did not exist. Created.
Lock acquired on [tangnano20k]
[Pipeline] {
[Pipeline] echo
Rodando teste na Nexys 4
[Pipeline] lock
Trying to acquire lock on [nexys4]
Resource [nexys4] did not exist. Created.
Lock acquired on [nexys4]
[Pipeline] {
[Pipeline] echo
FPGA ECP5 Broqueada
[Pipeline] sh
[Pipeline] echo
FPGA TangNano Broqueada
[Pipeline] sh
+ echo testando na ecp5
testando na ecp5
[Pipeline] echo
FPGA Nexys 4 Broqueada
+ echo testando na tang nano
testando na tang nano
[Pipeline] sh
[Pipeline] }
+ echo testando na tang nano
testando na tang nano
Lock released on resource [ecp5]
[Pipeline] }
Lock released on resource [tangnano20k]
[Pipeline] // lock
[Pipeline] // lock
[Pipeline] echo
ECP5 liberada
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] }
Lock released on resource [nexys4]
[Pipeline] // script
[Pipeline] // script
[Pipeline] // lock
[Pipeline] }
[Pipeline] }
[Pipeline] echo
TangNano liberada
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] // script
[Pipeline] }
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: SUCCESS
![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
