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Start of Pipeline - (29 sec in block)
node - (28 sec in block)
node block - (27 sec in block)
stage - (3.4 sec in block)Git Clone
stage block (Git Clone) - (2.9 sec in block)
sh - (0.48 sec in self)rm -Rf Risco-5/ build/
sh - (1.7 sec in self)git clone https://github.com/JN513/Risco-5
sh - (0.42 sec in self)cd Risco-5
stage - (3 sec in block)IVerilog
stage block (IVerilog) - (2.5 sec in block)
sh - (0.45 sec in self)mkdir -p build
sh - (0.46 sec in self)cp Risco-5/software/memory/add.hex Risco-5/software/memory/generic.hex
sh - (0.46 sec in self) /eda/oss-cad-suite/bin/iverilog -o build/soc_test.o -s soc_tb Risco-5/src/core/*.v Risco-5/src/peripheral/*.v Risco-5/tests/soc_test.v
sh - (0.5 sec in self)/eda/oss-cad-suite/bin/vvp build/soc_test.o
sh - (0.42 sec in self)rm -f Risco-5/software/memory/generic.hex
stage - (10 sec in block)Síntese
stage block (Síntese) - (9.5 sec in block)
parallel - (9 sec in block)
parallel block (Branch: OSS-Cad-Suite) - (67 ms in block)
stage - (5.1 sec in block)OSS-Cad-Suite
stage block (OSS-Cad-Suite) - (4.7 sec in block)
stage - (2.1 sec in block)Yosys
stage block (Yosys) - (1.3 sec in block)
sh - (0.76 sec in self) /eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/reset.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (0.99 sec in block)NextPNR
stage block (NextPNR) - (0.26 sec in block)
stage - (0.56 sec in block)ECPPACK
stage block (ECPPACK) - (0.24 sec in block)
parallel block (Branch: Gowin) - (67 ms in block)
stage - (6.4 sec in block)Gowin
stage block (Gowin) - (6 sec in block)
sh - (0.85 sec in self)rm -rf Risco-5/impl/pnr
sh - (0.79 sec in self)mkdir -p Risco-5/impl/pnr
sh - (3.6 sec in self)cd Risco-5/fpga/tangnano20k/ && /eda/gowin/IDE/bin/gw_sh run.tcl
parallel block (Branch: Vivado) - (8.1 sec in block)
stage - (7.1 sec in block)Vivado
stage block (Vivado) - (6.8 sec in block)
sh - (6.1 sec in self)cd Risco-5/fpga/nexys4_ddr && mkdir build && /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source run.tcl
stage - (5 sec in block)FPGA Flash
stage block (FPGA Flash) - (4.4 sec in block)
parallel - (3.9 sec in block)
parallel block (Branch: openFPGAloader ECP5) - (67 ms in block)
stage - (1.5 sec in block)openFPGAloader ECP5
stage block (openFPGAloader ECP5) - (0.77 sec in block)
parallel block (Branch: openFPGAloader Tangnano 20k) - (67 ms in block)
stage - (1.5 sec in block)openFPGAloader Tangnano 20k
stage block (openFPGAloader Tangnano 20k) - (0.76 sec in block)
parallel block (Branch: openFPGAloader Nexys 4 DDR) - (2.8 sec in block)
stage - (1.5 sec in block)openFPGAloader Nexys 4 DDR
stage block (openFPGAloader Nexys 4 DDR) - (0.75 sec in block)
stage - (5.3 sec in block)Testes
stage block (Testes) - (4.9 sec in block)
parallel - (4.5 sec in block)
parallel block (Branch: ECP5 - Testes) - (57 ms in block)
stage - (1.8 sec in block)ECP5 - Testes
stage block (ECP5 - Testes) - (0.82 sec in block)
parallel block (Branch: TangNano - Testes) - (56 ms in block)
stage - (2.1 sec in block)TangNano - Testes
stage block (TangNano - Testes) - (0.87 sec in block)
parallel block (Branch: Nexys 4 - Testes) - (3.5 sec in block)
stage - (2.1 sec in block)Nexys 4 - Testes
stage block (Nexys 4 - Testes) - (0.85 sec in block)