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Step	Arguments			Status
Start of Pipeline - (36 sec in block)
node - (36 sec in block)
node block - (35 sec in block)
stage - (2.1 sec in block)	git_clone
stage block (git_clone) - (1.8 sec in block)
sh - (0.39 sec in self)	rm -Rf Risco-5/ build/
sh - (0.91 sec in self)	git clone https://github.com/JN513/Risco-5
sh - (0.38 sec in self)	cd Risco-5
stage - (15 sec in block)	Yosys
stage block (Yosys) - (15 sec in block)
sh - (0.41 sec in self)	mkdir -p build
sh - (14 sec in self)	/eda/oss-cad-suite/bin/yosys -p " read_verilog Risco-5/fpga/ecp5/*.v; read_verilog Risco-5/debug/clk_divider.v; read_verilog Risco-5/src/core/*.v; read_verilog Risco-5/src/peripheral/*.v; synth_ecp5 -json ./build/out.json -abc9 "
stage - (17 sec in block)	NextPNR
stage block (NextPNR) - (16 sec in block)
sh - (16 sec in self)	/eda/oss-cad-suite/bin/nextpnr-ecp5 --json ./build/out.json --write ./build/out_pnr.json --45k --lpf Risco-5/fpga/ecp5/pinout.lpf --textcfg ./build/out.config --package CABGA381 --speed 6
stage - (0.48 sec in block)	ECPPACK
stage block (ECPPACK) - (0.11 sec in block)
stage - (0.33 sec in block)	openFPGAloader
stage block (openFPGAloader) - (0.13 sec in block)