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Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/airisc_core_complex
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf airisc_core_complex
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/Fraunhofer-IMS/airisc_core_complex airisc_core_complex
Cloning into 'airisc_core_complex'...
Submodule 'external/elf2hex' (https://github.com/sifive/elf2hex.git) registered for path 'external/elf2hex'
Submodule 'external/neoTRNG' (https://github.com/stnolting/neoTRNG.git) registered for path 'external/neoTRNG'
Submodule 'external/riscv-tests' (https://github.com/riscv-software-src/riscv-tests.git) registered for path 'external/riscv-tests'
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/elf2hex'...
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/neoTRNG'...
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/riscv-tests'...
Submodule path 'external/elf2hex': checked out 'f28a3103c06131ed3895052b1341daf4ca0b1c9c'
Submodule path 'external/neoTRNG': checked out '9889e484295b47b8d12972f732e126b26d0da7de'
Submodule path 'external/riscv-tests': checked out '96403c8facf128564e7828d37daee948147bfad0'
Submodule 'env' (https://github.com/riscv/riscv-test-env.git) registered for path 'external/riscv-tests/env'
Cloning into '/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/external/riscv-tests/env'...
Submodule path 'external/riscv-tests/env': checked out '4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46'
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] echo
simulation not supported for mixed VHDL and Verilog files
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
WARNING: Error writing to JSON file: [Errno 2] No such file or directory: '/jenkins/processor_ci_utils/labels.json'
Trying to read file: /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
Resource [colorlight_i9] did not exist. Created.
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] dir
Running in /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/build_colorlight_i9.tcl
Error executing Makefile.
ERROR: Can't open include file `airi5c_hasti_constants.vh'!
make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 218, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] echo
Starting synthesis for FPGA digilent_nexys4_ddr.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b digilent_nexys4_ddr
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
Stage "Flash colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
Stage "Test colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/build_digilent_nexys4_ddr.tcl
Error executing Makefile.
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_CmodA7/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_CmodA7/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_NexysVideo/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_NexysVideo/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-9263] cannot open include file 'modules/airi5c_fpu/airi5c_FPU_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_fpu/airi5c_ftoi_converter.v:14]
ERROR: [Synth 8-9263] cannot open include file 'modules/airi5c_fpu/airi5c_FPU_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_fpu/airi5c_post_processing.v:14]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_spi/src/airi5c_spi.v:14]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_trng/src/airi5c_trng.v:21]
ERROR: [Synth 8-9263] cannot open include file 'modules/airi5c_uart/src/airi5c_uart_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/src/modules/airi5c_uart/src/airi5c_uart.v:14]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_hasti_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:16]
ERROR: [Synth 8-9263] cannot open include file 'airi5c_dmi_constants.vh' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:17]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_ADDR_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:85]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_SIZE_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:87]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_BURST_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:88]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_PROT_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:90]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_TRANS_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:91]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_BUS_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:92]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_RESP_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:95]
ERROR: [Synth 8-10157] use of undefined macro 'DMI_ADDR_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:109]
ERROR: [Synth 8-10157] use of undefined macro 'DMI_WIDTH' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:110]
ERROR: [Synth 8-10157] use of undefined macro 'HASTI_RESP_OKAY' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:208]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:208]
ERROR: [Synth 8-2716] syntax error near ';' [/var/jenkins_home/workspace/airisc_core_complex/airisc_core_complex/fpga/src_ArtyA7/verilog/FPGA_Top.v:210]
ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/airisc_core_complex.v:48]
ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/airisc_core_complex.v:1]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 218, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_nexys4_ddr)
Stage "Test digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 283ddc6f-4aca-4557-af58-021267ccc74a
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE