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Start of Pipeline - (1 min 46 sec in block)
node - (1 min 44 sec in block)
node block - (1 min 43 sec in block)
stage - (9.7 sec in block)Git Clone
stage block (Git Clone) - (8.7 sec in block)
sh - (0.66 sec in self)rm -rf airisc_core_complex
sh - (7.7 sec in self)git clone --recursive --depth=1 https://github.com/Fraunhofer-IMS/airisc_core_complex airisc_core_complex
stage - (2.8 sec in block)Simulation
stage block (Simulation) - (1.8 sec in block)
dir - (1 sec in block)airisc_core_complex
dir block - (0.61 sec in block)
echo - (0.23 sec in self)simulation not supported for mixed VHDL and Verilog files
stage - (2.9 sec in block)Utilities
stage block (Utilities) - (2 sec in block)
dir - (1.3 sec in block)airisc_core_complex
dir block - (0.93 sec in block)
sh - (0.51 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (1 min 25 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (1 min 24 sec in block)
parallel - (1 min 23 sec in block)
parallel block (Branch: colorlight_i9) - (0.1 sec in block)
stage - (15 sec in block)colorlight_i9
stage block (colorlight_i9) - (15 sec in block)
lock - (13 sec in block)colorlight_i9
lock block - (12 sec in block)
stage - (5.6 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (4.4 sec in block)
dir - (2.9 sec in block)airisc_core_complex
dir block - (2.4 sec in block)
echo - (0.32 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (1.3 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b colorlight_i9
stage - (4 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (2.8 sec in block)
getContext - (1 sec in self)
stage - (0.83 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.4 sec in block)
getContext - (0.16 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (1 min 22 sec in block)
stage - (1 min 21 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (1 min 20 sec in block)
lock - (1 min 18 sec in block)digilent_nexys4_ddr
lock block - (1 min 17 sec in block)
stage - (1 min 12 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (1 min 11 sec in block)
dir - (1 min 10 sec in block)airisc_core_complex
dir block - (1 min 9 sec in block)
echo - (0.35 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (1 min 8 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p airisc_core_complex -b digilent_nexys4_ddr
stage - (1.8 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.72 sec in block)
getContext - (0.33 sec in self)
stage - (1.3 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.75 sec in block)
getContext - (0.33 sec in self)
stage - (1.5 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.53 sec in self)**/test-reports/*.xml