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Start of Pipeline - (9 min 29 sec in block)
node - (9 min 29 sec in block)
node block - (9 min 28 sec in block)
stage - (6.7 sec in block)Git Clone
stage block (Git Clone) - (6.2 sec in block)
sh - (0.47 sec in self)rm -rf e203_hbirdv2
sh - (5.5 sec in self)git clone --recursive --depth=1 https://github.com/riscv-mcu/e203_hbirdv2 e203_hbirdv2
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.4 sec in block)
dir - (1 sec in block)e203_hbirdv2
dir block - (0.79 sec in block)
sh - (0.6 sec in self)
stage - (1.6 sec in block)Utilities
stage block (Utilities) - (1.1 sec in block)
dir - (0.84 sec in block)e203_hbirdv2
dir block - (0.59 sec in block)
sh - (0.39 sec in self)python3 /eda/processor_ci/core/labeler_prototype.py -d $(pwd) -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
stage - (9 min 17 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (9 min 16 sec in block)
parallel - (9 min 16 sec in block)
parallel block (Branch: colorlight_i9) - (76 ms in block)
stage - (9 min 15 sec in block)colorlight_i9
stage block (colorlight_i9) - (9 min 14 sec in block)
lock - (9 min 13 sec in block)colorlight_i9
lock block - (7.8 sec in block)
stage - (4.3 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (3.1 sec in block)
dir - (2.3 sec in block)e203_hbirdv2
dir block - (1.7 sec in block)
echo - (0.34 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (1 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p e203_hbirdv2 -b colorlight_i9
stage - (1.8 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.75 sec in block)
getContext - (0.35 sec in self)
stage - (0.95 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (0.59 sec in block)
getContext - (0.19 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (32 sec in block)
stage - (32 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (31 sec in block)
lock - (31 sec in block)digilent_nexys4_ddr
lock block - (30 sec in block)
stage - (28 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (27 sec in block)
dir - (27 sec in block)e203_hbirdv2
dir block - (27 sec in block)
echo - (0.16 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (26 sec in self)python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p e203_hbirdv2 -b digilent_nexys4_ddr
stage - (0.96 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (0.38 sec in block)
getContext - (0.16 sec in self)
stage - (0.66 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.36 sec in block)
getContext - (0.15 sec in self)
stage - (0.76 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (0.5 sec in block)
junit - (0.26 sec in self)**/test-reports/*.xml