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Start of Pipeline - (1 min 23 sec in block)
node - (1 min 21 sec in block)
node block - (1 min 21 sec in block)
stage - (3 sec in block)Git Clone
stage block (Git Clone) - (2.5 sec in block)
sh - (0.49 sec in self)rm -rf tinyriscv
sh - (1.7 sec in self)git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv
stage - (1.8 sec in block)Simulation
stage block (Simulation) - (1.3 sec in block)
dir - (0.92 sec in block)tinyriscv
dir block - (0.63 sec in block)
sh - (0.43 sec in self)/eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v
stage - (2 sec in block)Utilities
stage block (Utilities) - (1.2 sec in block)
dir - (0.86 sec in block)tinyriscv
dir block - (0.61 sec in block)
sh - (0.39 sec in self)python3 /eda/processor-ci/labeler_prototype.py -d $(pwd) -c /eda/processor-ci/config.json -o /jenkins/processor-ci_utils/labels.json
stage - (1 min 12 sec in block)FPGA Build Pipeline
stage block (FPGA Build Pipeline) - (1 min 11 sec in block)
parallel - (1 min 10 sec in block)
parallel block (Branch: colorlight_i9) - (0.11 sec in block)
stage - (1 min 4 sec in block)colorlight_i9
stage block (colorlight_i9) - (1 min 3 sec in block)
lock - (1 min 1 sec in block)colorlight_i9
lock block - (55 sec in block)
stage - (50 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (49 sec in block)
dir - (48 sec in block)tinyriscv
dir block - (47 sec in block)
echo - (0.35 sec in self)Starting synthesis for FPGA colorlight_i9.
sh - (47 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9
stage - (2.3 sec in block)Flash colorlight_i9
stage block (Flash colorlight_i9) - (0.54 sec in block)
getContext - (0.33 sec in self)
stage - (2.2 sec in block)Test colorlight_i9
stage block (Test colorlight_i9) - (1.1 sec in block)
getContext - (0.24 sec in self)
parallel block (Branch: digilent_nexys4_ddr) - (1 min 9 sec in block)
stage - (1 min 7 sec in block)digilent_nexys4_ddr
stage block (digilent_nexys4_ddr) - (1 min 7 sec in block)
lock - (1 min 5 sec in block)digilent_nexys4_ddr
lock block - (59 sec in block)
stage - (52 sec in block)Synthesis and PnR
stage block (Synthesis and PnR) - (49 sec in block)
dir - (49 sec in block)tinyriscv
dir block - (48 sec in block)
echo - (0.34 sec in self)Starting synthesis for FPGA digilent_nexys4_ddr.
sh - (47 sec in self)python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr
stage - (4.3 sec in block)Flash digilent_nexys4_ddr
stage block (Flash digilent_nexys4_ddr) - (1.6 sec in block)
getContext - (0.32 sec in self)
stage - (1.3 sec in block)Test digilent_nexys4_ddr
stage block (Test digilent_nexys4_ddr) - (0.8 sec in block)
getContext - (0.33 sec in self)
stage - (1.4 sec in block)Declarative: Post Actions
stage block (Declarative: Post Actions) - (1 sec in block)
junit - (0.52 sec in self)**/test-reports/*.xml